Integration of copper with an organic low-k dielectric in 0.12-μm node interconnect
FAYOLLE, M, PASSEMARD, G, ASSOUS, M, LOUIS, D, BEVERINA, A, GOBIL, Y, CLUZEL, J, ARNAUD, L
Published in Microelectronic engineering (2002)
Published in Microelectronic engineering (2002)
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Journal Article
Cleaning status on low- k dielectric in advanced VLSI interconnect: : Characterisation and principal issues
Louis, D, Beverina, A, Arvet, C, Lajoinie, E, Peyne, C, Holmes, D, Maloney, D
Published in Microelectronic engineering (01.09.2001)
Published in Microelectronic engineering (01.09.2001)
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Journal Article
New concept of high- k integration in MOSFET’s by a deposition through contact holes
Harrison, S, Coronel, P, Wacquant, F, Regnier, C, Leverd, F, Beverina, A, Bustos, J, Tavel, B, Skotnicki, T
Published in Microelectronic engineering (01.04.2004)
Published in Microelectronic engineering (01.04.2004)
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Conference Proceeding
Overview of Cu contamination during integration in a dual damascene architecture for sub-quarter micron technology
Torres, J, Palleau, J, Tardif, F, Bernard, H, Beverina, A, Motte, P, Pantel, R, Juhel, M
Published in Microelectronic engineering (2000)
Published in Microelectronic engineering (2000)
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Journal Article
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Nickel vs. cobalt silicide integration for sub-50nm CMOS
Froment, B., Muller, M., Brut, H., Pantel, R., Carron, V., Achard, H., Halimaoui, A., Boeuf, F., Wacquant, F., Regnier, C., Ceccarelli, D., Palla, R., Beverina, A., DeJonghe, V., Spinelli, P., Leborgne, O., Bard, K., Lis, S., Tirard, V., Morin, P., Trentesaux, F., Gravey, V., Mandrekar, T., Rabilloud, D., Van, S., Olson, E., Diedrick, J.
Published in ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003 (2003)
Published in ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003 (2003)
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Conference Proceeding
Silicon clean impact on 90nm CMOS devices performance
Carrere, J.-P., Bernard, H., Petitdidier, S., Beverina, A., Rosa, J., Guyader, F.
Published in ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003 (2003)
Published in ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003 (2003)
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Conference Proceeding
Triple Gate Oxide by nitrogen implantation integrated in a 0.13μm CMOS flow
CARRERE, J-P, GROUILLET, A, GUYADER, F, BEVERINA, A, BIDAUD, M, HALIMAOUI, A
Year of Publication 2002
Year of Publication 2002
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Low cost 65nm CMOS platform for Low Power & General Purpose applications
Arnaud, F., Duriez, B., Tavel, B., Pain, L., Todeschini, J., Jurdit, M., Laplanche, Y., Boeuf, F., Salvetti, F., Lenoble, D., Reynard, J.P., Wacquant, F., Morin, P., Emonet, N., Barge, D., Bidaud, M., Ceccarelli, D., Vannier, P., Loquet, Y., Leninger, H., Judong, F., Perrot, C., Guilmeau, I., Palla, R., Beverina, A., DeJonghe, V., Broekaart, M., Vachellerie, V., Bianchi, R.A., Borot, B., Devoivre, T., Bicais, N., Roy, D., Denais, M., Rochereau, K., Difrenza, R., Planes, N., Brut, H., Vishnobulta, L., Reber, D., Stolk, P., Woo, M.
Published in Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004 (2004)
Published in Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004 (2004)
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Conference Proceeding
Poly-gate replacement through contact hole (PRETCH): a new method for high-k/metal gate and multi-oxide implementation on chip
Harrison, S., Coronel, P., Cros, A., Cerutti, R., Leverd, F., Beverina, A., Wacquez, R., Bustos, J., Delille, D., Tavel, B., Barge, D., Bienacel, J., Samson, M.P., Martin, F., Maitrejean, S., Munteanu, D., Autran, J.L., Skotnicki, T.
Published in IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004 (2004)
Published in IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004 (2004)
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Conference Proceeding
Cleaning process strategies compatible with low-k dielectric and copper: state of the art, evolution and perspectives
Louis, D., Beverina, A., Arvet, C., Lajoinie, E., Peyne, C., Holmes, D., Maloney, D., Lee, S., Lee, W.M.
Published in Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407) (2000)
Published in Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407) (2000)
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Conference Proceeding
Copper-silk integration in a 0.18μm double level metal interconnect
DEMOLLIENS, O, BERRUYER, P, LOUIS, D, ARVET, C, LAJOINIE, E, GOBIL, Y, PASSEMARD, G, JOURDAN, F, MOUSSAVI, M, CORDEAU, M, MOREL, T, MOURIER, T, MORAND, Y, ULMER, L, SICURANI, E, TARDIF, F, BEVERINA, A, TROUILLET, Y, RENAUD, D, TABONE, C, ROMAN, A, COCHET, M, ASSOUS, M, FELDIS, H, BLANC, R, TABOURET, E
Year of Publication 1999
Year of Publication 1999
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Conference Proceeding
Cleaning status on low-k dielectric in advanced VLSI interconnect
Louis, D, Beverina, A, Arvet, C, Lajoinie, E, Peyne, C, Holmes, D, Maloney, D
Published in Microelectronic engineering (01.09.2001)
Published in Microelectronic engineering (01.09.2001)
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Journal Article
65 nm Device Manufacture Using Shaped E-Beam Lithography
Pain, Laurent, Jurdit, Murielle, Laplanche, Yves, Todeschini, Jérôme, Leininger, Hugues, Tourniol, Sonia, Faure, Romuald, Bossy, Xavier, Palla, Ramiro, Beverina, Alessio, Broekaart, Marcel, Judong, Fabienne, Brosselin, Karine, Depoyan, Linda, Friec, Yannick Le, Leverd, Francois, Jonghe, Veronique De, Josse, Emmanuelle, Hinsinger, Olivier, Brun, Philippe, Henry, Daniel, Woo, Michael, Stolk, Peter, Tavel, Brice, Arnaud, Franck
Published in Japanese Journal of Applied Physics (01.06.2004)
Published in Japanese Journal of Applied Physics (01.06.2004)
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Journal Article
Overview of Cu contamination during integration in a dual damascene architecture for sub-quarter micron technology
Torres, J, Palleau, J, Tardif, F, Bernard, H, Beverina, A, Motte, P, Pantel, R, Juhel, M
Published in Microelectronic engineering (07.03.1999)
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Published in Microelectronic engineering (07.03.1999)
Journal Article
Cleaning status on low-κ dielectric in advanced VLSI interconnect : Characterisation and principal issues
LOUIS, D, BEVERINA, A, ARVET, C, LAJOINIE, E, PEYNE, C, HOLMES, D, MALONEY, D
Published in Microelectronic engineering (2001)
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Published in Microelectronic engineering (2001)
Conference Proceeding
Triple Gate Oxide by Nitrogen Implantation Integrated in a 0.13um CMOS Flow
Carrere, J.P., Grouillet, A., Guyader, F., Beverina, A., Bidaud, M., Halimaoui, A.
Published in 32nd European Solid-State Device Research Conference (2002)
Published in 32nd European Solid-State Device Research Conference (2002)
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Conference Proceeding
New junction concepts for sub-50 nm CMOS transistors: slim spacers and Ni silicide
Muller, M., Froment, B., Carron, V., Beverina, A., Palla, R., Pantel, R., Morin, P., Charbuillet, C., Pouydebasque, A., Boeuf, F., Skotnicki, T.
Published in ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003 (2003)
Published in ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003 (2003)
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Conference Proceeding
65 nm device manufacture using shaped E-Beam lithography
Pain, L., Charpin, M., Laplanche, Y., Todeschini, J., Leininger, H., Tourniol, S., Faure, R., Bossy, X., Palla, R., Beverina, A., Broekaart, M., Judong, F., Brosselin, K., Le Friec, Y., Leverd, F., De Jonghe, V., Josse, E., Hinsinger, O., Brun, P., Henry, D., Woo, M., Stolk, P., Arnaud, F.
Published in Digest of Papers Microprocesses and Nanotechnology 2003. 2003 International Microprocesses and Nanotechnology Conference (2003)
Published in Digest of Papers Microprocesses and Nanotechnology 2003. 2003 International Microprocesses and Nanotechnology Conference (2003)
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Conference Proceeding
Low cost 65nm CMOS platform for low power & general purpose applications
ARNAUD, F, DURIEZ, B, REYNARD, J. P, WACQUANT, F, MORIN, P, EMONET, N, BARGE, D, BIDAUD, M, CECCARELLI, D, VANNIER, P, LOQUET, Y, LENINGER, H, TAVEL, B, JUDONG, F, PERROT, C, GUILMEAU, I, PALLA, R, BEVERINA, A, DEJONGHE, V, BROEKAART, M, VACHELLERIE, V, BIANCHI, R. A, BOROT, B, PAIN, L, DEVOIVRE, T, BICAÏS, N, ROY, D, DENAIS, M, ROCHEREAU, K, DIFRENZA, R, PLANES, N, BRUT, H, VISHNOBULTA, L, REBER, D, TODESCHINI, J, STALK, P, WOE, M, JURDIT, M, LAPLANCHE, Y, BOEUF, F, SALVETTI, F, LENOBLE, D
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