Computing the entire active area/power consumption versus delay tradeoff curve for gate sizing with a piecewise linear simulator
Berkelaar, M.R.C.M., Buurman, P.H.W., Jess, J.A.G.
Published in IEEE transactions on computer-aided design of integrated circuits and systems (01.11.1996)
Published in IEEE transactions on computer-aided design of integrated circuits and systems (01.11.1996)
Get full text
Journal Article
An efficient divide and conquer algorithm for exact hazard free logic minimization
Rutten, J. W. J. M., Berkelaar, M. R. C. M., van Eijk, C. A. J., Kolsteren, M. A. J.
Published in Proceedings of the conference on Design, automation and test in Europe (23.02.1998)
Published in Proceedings of the conference on Design, automation and test in Europe (23.02.1998)
Get full text
Conference Proceeding
Gate sizing in MOS digital circuits with linear programming
Berkelaar, Michel R. C. M., Jess, Jochen A. G.
Published in Proceedings of the conference on European design automation (12.03.1990)
Published in Proceedings of the conference on European design automation (12.03.1990)
Get full text
Conference Proceeding