Search Results - "Barth, Jr. John E" :: K.UTB vyhledávací portál | TBU Library Retrieval Portal

Array organization and architecture to perform range-match operations with content addressable memory (CAM) circuits

Array organization and architecture to perform range-match operations with content addressable memory (CAM) circuits

by Barth, Jr., John E, Lewis, Dean L
Year of Publication 23.03.2021

Get full text

Patent

Array organization and architecture to perform range-match operations with content addressable memory (CAM) circuits

Array organization and architecture to perform range-match operations with content addressable memory (CAM) circuits

by Barth, Jr., John E, Lewis, Dean L
Year of Publication 01.10.2019

Get full text

Patent

Providing transposable access to a synapse array using a recursive array layout

Providing transposable access to a synapse array using a recursive array layout

by Barth, Jr., John E, Merolla, Paul A, Arthur, John V, Modha, Dharmendra S
Year of Publication 27.07.2021

Get full text

Patent

Vertically integrated memory cell

Vertically integrated memory cell

by Khan Babar A, Barth, Jr. John E
Year of Publication 14.02.2017

Get full text

Patent

Vertically integrated memory cell

Vertically integrated memory cell

by Khan Babar A, Barth, Jr. John E
Year of Publication 11.10.2016

Get full text

Patent

VDD pre-set of direct sense DRAM

VDD pre-set of direct sense DRAM

by Barth, Jr, John E
Year of Publication 07.08.2012

Get full text

Patent

Capacitively isolated mismatch compensated sense amplifier

Capacitively isolated mismatch compensated sense amplifier

by Barth, Jr, John E
Year of Publication 06.09.2011

Get full text

Patent

Transforming local threading resistance to global distributed resistance

Transforming local threading resistance to global distributed resistance

by LANAHAN MICHAEL C, HERBERT JOHN, BARTH, JOHN, E., JR
Year of Publication 18.08.2023

Get full text

Patent

Interconnect circuits at three-dimensional (3-D) bonding interfaces of a processor array

Interconnect circuits at three-dimensional (3-D) bonding interfaces of a processor array

by Sawada, Jun, Barth, Jr., John E, Cassidy, Andrew S, Iyer, Subramanian S, Jackson, Bryan L, Merolla, Paul A, Arthur, John V, Rivera, Rodrigo Alvarez-Icaza, Modha, Dharmendra S
Year of Publication 11.08.2020

Get full text

Patent

Memory cell access circuit

Memory cell access circuit

by Barth, Jr, John E
Year of Publication 06.04.2010

Get full text

Patent

Vertical fin eDRAM

Vertical fin eDRAM

by Anderson Brent A, Nowak Edward J, Barth, Jr. John E
Year of Publication 13.09.2016

Get full text

Patent

Providing transposable access to a synapse array using a recursive array layout

Providing transposable access to a synapse array using a recursive array layout

by Barth, Jr., John E, Merolla, Paul A, Arthur, John V, Modha, Dharmendra S
Year of Publication 08.05.2018

Get full text

Patent

CAPACITIVELY ISOLATED MISMATCH COMPENSATED SENSE AMPLIFIER

CAPACITIVELY ISOLATED MISMATCH COMPENSATED SENSE AMPLIFIER

by BARTH, JOHN, E., JR
Year of Publication 23.04.2014

Get full text

Patent

Memory cell access circuit

Memory cell access circuit

by Barth, Jr, John E
Year of Publication 11.03.2008

Get full text

Patent

CAPACITIVELY ISOLATED MISMATCH COMPENSATED SENSE AMPLIFIER

CAPACITIVELY ISOLATED MISMATCH COMPENSATED SENSE AMPLIFIER

by BARTH, JOHN, E., JR
Year of Publication 12.12.2012

Get full text

Patent

System and method for capacitive mis-match bit-line sensing

System and method for capacitive mis-match bit-line sensing

by Barth, Jr, John E
Year of Publication 23.10.2007

Get full text

Patent

Faulty core recovery mechanisms for a three-dimensional network on a processor array

Faulty core recovery mechanisms for a three-dimensional network on a processor array

by Barth, Jr., John E, Cassidy, Andrew S, Iyer, Subramanian, Merolla, Paul A, Arthur, John V, Alvarez-Icaza Rivera, Rodrigo, Modha, Dharmendra S
Year of Publication 08.01.2019

Get full text

Patent

Deep trench electrostatic discharge (ESD) protect diode for silicon-on-insulator (SOI) devices

Deep trench electrostatic discharge (ESD) protect diode for silicon-on-insulator (SOI) devices

by Barth, Jr, John E, Bernstein, Kerry
Year of Publication 11.09.2012

Get full text

Patent

Dynamic random access memory cell with self-aligned strap

Dynamic random access memory cell with self-aligned strap

by Vega Reinaldo A, Cheng Kangguo, Ramachandran Ravikumar, Barth, Jr. John E, Rim Kern, Ho Herbert L, Khakifirooz Ali
Year of Publication 15.08.2017

Get full text

Patent

Design structure including failing address register and compare logic for multi-pass repair of memory arrays

Design structure including failing address register and compare logic for multi-pass repair of memory arrays

by Barth, Jr, John E, Sliva, Stephen F
Year of Publication 06.03.2012

Get full text

Patent

1
2
3
4
5
6
7
8
9
10
11
Next
[11]