Design exploration of IGZO diode based VCMA array design for Storage Class Memory Applications
Gupta, M., Perumkunnil, M., Fantini, A., Chamazcoti, S. A., Kim, W., Bardon, M.G., Kar, G.S., Furnemont, A.
Published in ESSDERC 2022 - IEEE 52nd European Solid-State Device Research Conference (ESSDERC) (19.09.2022)
Published in ESSDERC 2022 - IEEE 52nd European Solid-State Device Research Conference (ESSDERC) (19.09.2022)
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Conference Proceeding
Pseudo-Two-Dimensional Model for Double-Gate Tunnel FETs Considering the Junctions Depletion Regions
Bardon, M.G., Neves, H.P., Puers, R., Van Hoof, C.
Published in IEEE transactions on electron devices (01.04.2010)
Published in IEEE transactions on electron devices (01.04.2010)
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Journal Article
Scaling the Suspended-Gate FET: Impact of Dielectric Charging and Roughness
Bardon, M.G., Neves, H.P., Puers, R., Van Hoof, C.
Published in IEEE transactions on electron devices (01.04.2010)
Published in IEEE transactions on electron devices (01.04.2010)
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Journal Article
Circuit Design for Bias Compatibility in Novel FinFET-Based Floating-Body RAM
Poliakov, P., Anchlia, A., Bardon, M.G., Rooseleer, B., De Wachter, B., Collaert, N., van der Zanden, K., Dehaene, W., Verkest, D., Corbalan, M.M.
Published in IEEE transactions on circuits and systems. II, Express briefs (01.03.2010)
Published in IEEE transactions on circuits and systems. II, Express briefs (01.03.2010)
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Journal Article