Search Results - "BUPESH PANDITA" :: K.UTB vyhledávací portál

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PROGRAMMABLE ANALOG CALIBRATION CIRCUIT SUPPORTING ITERATIVE MEASUREMENT OF AN INPUT SIGNAL FROM A CIRCUIT BY

by PANDITA BUPESH, BANERJEE ANINDYA, BOCK CHRISTIAN, GROEN, ERWIN
Year of Publication 05.04.2024

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Low-power, low-latency time-to-digital-converter-based serial link

by Hailu, Eskinder, Pandita, Bupesh, Jun, Yong Suk, Zhu, Zhi, Chen, Minhan, Goudarzi, Hadi, Boyette, Jon
Year of Publication 30.03.2021

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APPARATUS AND METHOD FOR COMBINING CURRENTS FROM PASSIVE EQUALIZER IN SENSE AMPLIFIER

by HAILU, Eskinder, PANDITA, Bupesh, COHEN, Hanan
Year of Publication 20.04.2017

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A GATE BOOSTED LOW DROP REGULATOR

by PANDITA BUPESH, GAO ZHUO
Year of Publication 21.12.2018

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APPARATUS AND METHOD FOR COMBINING CURRENTS FROM PASSIVE EQUALIZER IN SENSE AMPLIFIER

by Hailu Eskinder, Pandita Bupesh, Cohen Hanan
Year of Publication 13.04.2017

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Apparatus and method for combining currents from passive equalizer in sense amplifier

by Hailu Eskinder, Pandita Bupesh, Cohen Hanan
Year of Publication 21.03.2017

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PHASE LOCKED LOOP (PLL) ARCHITECTURE

by PANDITA, Bupesh, ARCUDIA, Kenneth Luis, SHAFER, Jeffrey Andrew
Year of Publication 02.01.2019

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Phase-locked-loop circuit employing a hybrid loop filter with sample and hold capacitors for reduced signal jitter, and related methods

by BOECKER, CHARLES, PANDITA, BUPESH, LU, PING
Year of Publication 16.07.2023

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BUILT-IN TEST STRUCTURE FOR A RECEIVER

by Arcudia Kenneth Luis, Chen Minhan, Pandita Bupesh
Year of Publication 28.07.2016

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LOW-POWER, LOW-LATENCY TIME-TO-DIGITAL-CONVERTER-BASED SERIAL LINK

by Hailu, Eskinder, Pandita, Bupesh, Jun, Yong Suk, Zhu, Zhi, Chen, Minhan, Goudarzi, Hadi, Boyette, Jon
Year of Publication 02.04.2020

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APPARATUS AND METHOD FOR IN SITU ANALOG SIGNAL DIAGNOSTIC AND DEBUGGING WITH CALIBRATED ANALOG-TO-DIGITAL CONVERTER

by SONG, Deqiang, KONG, Xiaohua, PANDITA, Bupesh, GAO, Zhuo
Year of Publication 08.03.2018

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PHASE LOCKED LOOP (PLL) ARCHITECTURE

by PANDITA, Bupesh, ARCUDIA, Kenneth Luis, SHAFER, Jeffrey Andrew
Year of Publication 17.01.2018

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Apparatus and method for in situ analog signal diagnostic and debugging with calibrated analog-to-digital converter

by Gao Zhuo, Song Deqiang, Kong Xiaohua, Pandita Bupesh
Year of Publication 08.08.2017

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Fractional phase locked loop (PLL) architecture

by Arcudia Kenneth Luis, Hailu Eskinder, Pandita Bupesh, Cohen Hanan
Year of Publication 21.02.2017

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NEW FRACTIONAL PHASE LOCKED LOOP (PLL) ARCHITECTURE

by PANDITA, Bupesh, HAILU, Eskinder, COHEN, Hanan, ARCUDIA, Kenneth Luis
Year of Publication 16.02.2017

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NEW FRACTIONAL PHASE LOCKED LOOP (PLL) ARCHITECTURE

by Arcudia Kenneth Luis, Hailu Eskinder, Pandita Bupesh, Cohen Hanan
Year of Publication 09.02.2017

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Phase locked loop (PLL) architecture

by Arcudia Kenneth Luis, Shafer Jeffrey Andrew, Pandita Bupesh
Year of Publication 01.11.2016

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SERDES WITH ADAPTIVE CLOCK DATA RECOVERY

by PANDITA BUPESH, BOYETTE JON, HAILU ESKINDER
Year of Publication 11.02.2020

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NOVEL PHASE LOCKED LOOP (PLL) ARCHITECTURE

by Arcudia Kenneth Luis, Shafer Jeffrey Andrew, Pandita Bupesh
Year of Publication 15.09.2016

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PHASE LOCKED LOOP (PLL) ARCHITECTURE

by PANDITA, Bupesh, ARCUDIA, Kenneth Luis, SHAFER, Jeffrey Andrew
Year of Publication 15.09.2016

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