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"BUCH; KIRAN B"
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"BUCH; KIRAN B"
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Test methodology based on multiple skewed scan clocks
by
BUCH
;
KIRAN B
,
VASHI; MEHUL R
Year of Publication
30.05.2000
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Programmable IC with gate array core and boundary scan capability
by
BUCH KIRAN B
,
LAW EDWIN S
,
BAXTER GLENN A
Year of Publication
01.05.2001
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Programmable I/O cell with dual boundary scan
by
BUCH
;
KIRAN B
,
BAXTER; GLENN A
,
LAW; EDWIN S
Year of Publication
06.06.2000
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Mask-programmed integrated circuits having timing and logic compatibility to user-configured logic arrays
by
BUCH
;
KIRAN B
,
CHU; JAKONG J
,
LAW; EDWIN S
Year of Publication
27.08.1996
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Hardwire logic device emulating any of two or more FPGAs
by
BUCH KIRAN B
,
LAW EDWIN S
,
BAXTER GLENN A
,
PANG RAYMOND C
Year of Publication
05.03.2002
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Hardwire logic device emulating any of two or more FPGAs
by
Law, Edwin S
,
Buch
,
Kiran B
,
Baxter, Glenn A
,
Pang, Raymond C
Year of Publication
05.03.2002
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MASK-PROGRAMMED INTEGRATED CIRCUITS HAVING TIMING AND LOGIC COMPATIBILITY TO USER-CONFIGURED LOGIC ARRAYS
by
CHU, JAKONG, J
,
BUCH
,
KIRAN
,
B
,
LAW, EDWIN, S
Year of Publication
24.07.1996
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MASK-PROGRAMMED INTEGRATED CIRCUITS HAVING TIMING AND LOGIC COMPATIBILITY TO USER-CONFIGURED LOGIC ARRAYS
by
CHU, JAKONG, J
,
BUCH
,
KIRAN
,
B
,
LAW, EDWIN, S
Year of Publication
27.12.1995
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MASK-PROGRAMMED INTEGRATED CIRCUITS HAVING TIMING AND LOGIC COMPATIBILITY TO USER-CONFIGURED LOGIC ARRAYS
by
CHU, JAKONG, J
,
BUCH
,
KIRAN
,
B
,
LAW, EDWIN, S
Year of Publication
15.09.1994
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Method of implementing a boundary scan chain
by
PANG; RAYMOND C
,
BUCH
;
KIRAN B
,
BAXTER; GLENN A
,
LAW; EDWIN S
Year of Publication
17.10.2000
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Hardwire logic device emulating an FPGA
by
PANG; RAYMOND C
,
BUCH
;
KIRAN B
,
BAXTER; GLENN A
,
LAW; EDWIN S
Year of Publication
19.09.2000
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Boundary scan chain with dedicated programmable routing
by
PANG; RAYMOND C
,
BUCH
;
KIRAN B
,
BAXTER; GLENN A
,
LAW; EDWIN S
Year of Publication
23.11.1999
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