DRAM Refresh Mechanisms, Penalties, and Trade-Offs
Bhati, Ishwar, Mu-Tien Chang, Chishti, Zeshan, Shih-Lien Lu, Jacob, Bruce
Published in IEEE transactions on computers (01.01.2016)
Published in IEEE transactions on computers (01.01.2016)
Get full text
Journal Article
A role for the CXCR4-CXCL12 axis in the little skate, Leucoraja erinacea
Hersh, Taylor A, Dimond, Alexandria L, Ruth, Brittany A, Lupica, Noah V, Bruce, Jacob C, Kelley, John M, King, Benjamin L, Lutton, Bram V
Published in American journal of physiology. Regulatory, integrative and comparative physiology (01.08.2018)
Published in American journal of physiology. Regulatory, integrative and comparative physiology (01.08.2018)
Get full text
Journal Article
Editor-in-Chief
Abbott, Derek, Aissa, Sonia, Annaswamy, Anuradha, Ansari, Nirwan, Cai, Jun, Chen, Kun-Shan, Chen, Yixin, Chiao, J.-C., El-Baz, Ayman, Fattah, Shaikh, Gooi, Hoay, Gokhale, Maya, I, Chih-Lin, Iannaccone, Giuseppe, Iwashita, Yumi, Jacob, Bruce, Jamalipour, Abbas, Javidi, Bahram, Jiang, Weihua, Kaynak, Okyay, Kirkici, Hulya, Lambert-Torres, Germano, Li, Shengtao, Mrozowski, Michal, Nappi, Michele, Novak, Dalma, Proenca, Hugo, Qian, Yi, Qu, Zhihua, Rahardja, Susanto, Saif, Mehrdad, Serpenguzel, Ali, Siegel, Peter H., Trebi-Ollennu, Ashitey, Tuninetti, Daniela, Wang, Ge, Wear, Keith A., Weisshaar, Andreas, Yue, C. Patrick, Zio, Enrico
Published in IEEE access (2024)
Published in IEEE access (2024)
Get full text
Journal Article
DRAMsim3: A Cycle-Accurate, Thermal-Capable DRAM Simulator
Li, Shang, Yang, Zhiyuan, Reddy, Dhiraj, Srivastava, Ankur, Jacob, Bruce
Published in IEEE computer architecture letters (01.07.2020)
Published in IEEE computer architecture letters (01.07.2020)
Get full text
Journal Article
DRAMSim2: A Cycle Accurate Memory System Simulator
Rosenfeld, P, Cooper-Balis, E, Jacob, B
Published in IEEE computer architecture letters (01.01.2011)
Published in IEEE computer architecture letters (01.01.2011)
Get full text
Journal Article
Analyzing the Monolithic Integration of a ReRAM-Based Main Memory Into a CPU's Die
Jagasivamani, Meenatchi, Walden, Candace, Singh, Devesh, Kang, Luyi, Li, Shang, Asnaashari, Mehdi, Dubois, Sylvain, Jacob, Bruce, Yeung, Donald
Published in IEEE MICRO (01.11.2019)
Published in IEEE MICRO (01.11.2019)
Get full text
Journal Article
Technology comparison for large last-level caches (L3Cs): Low-leakage SRAM, low write-energy STT-RAM, and refresh-optimized eDRAM
Mu-Tien Chang, Rosenfeld, P., Shih-Lien Lu, Jacob, B.
Published in 2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA) (01.02.2013)
Published in 2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA) (01.02.2013)
Get full text
Conference Proceeding
An analytical model for designing memory hierarchies
Jacob, B.L., Chen, P.M., Silverman, S.R., Mudge, T.N.
Published in IEEE transactions on computers (01.10.1996)
Published in IEEE transactions on computers (01.10.1996)
Get full text
Journal Article
Coordinated refresh: Energy efficient techniques for DRAM refresh scheduling
Bhati, Ishwar, Chishti, Zeshan, Jacob, Bruce
Published in International Symposium on Low Power Electronics and Design (ISLPED) (01.09.2013)
Published in International Symposium on Low Power Electronics and Design (ISLPED) (01.09.2013)
Get full text
Conference Proceeding