Method for prediction of premature dielectric breakdown in a semiconductor
COWLEY ANDREW P, MCLAUGHLIN PAUL S, EDWARDS ROBERT D, RATHORE HAZARA S, BARILE CONRAD A, CLEVENGER LAWRENCE A, CHANDA KAUSHIK, YANG CHIHAO
Year of Publication 08.11.2011
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Year of Publication 08.11.2011
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METHOD FOR PREDICTION OF PREMATURE DIELECTRIC BREAKDOWN IN A SEMICONDUCTOR
COWLEY ANDREW P, MCLAUGHLIN PAUL S, EDWARDS ROBERT D, RATHORE HAZARA S, BARILE CONRAD A, CLEVENGER LAWRENCE A, CHANDA KAUSHIK, YANG CHIHAO
Year of Publication 24.07.2008
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Year of Publication 24.07.2008
Patent
METHOD FOR PREDICTION OF PREMATURE DIELECTRIC BREAKDOWN IN A SEMICONDUCTOR
COWLEY ANDREW P, MCLAUGHLIN PAUL S, EDWARDS ROBERT D, RATHORE HAZARA S, BARILE CONRAD A, CLEVENGER LAWRENCE A, CHANDA KAUSHIK, YANG CHIHAO
Year of Publication 14.12.2006
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Year of Publication 14.12.2006
Patent
Stacked via-stud with improved reliability in copper metallurgy
MURRAY CONAL E, ENGEL BRETT H, BARILE CONRAD A, LANE MICHAEL, RATHORE HAZARA S, DALAL HORMAZDYAR M, AGARWALA BIRENDRA N, LIU XIAO H, NGUYEN DU B, LEVINE ERNEST, SHAW THOMAS M, NAYAK JAWAHAR P, MCGAHAY VINCENT, MCGRATH JOHN F
Year of Publication 19.01.2006
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Year of Publication 19.01.2006
Patent
Stacked via-stud with improved reliability in copper metallurgy
Agarwala, Birendra N, Barile, Conrad A, Dalal, Hormazdyar M, Engle, Brett H, Lane, Michael, Levine, Ernest, Liu, Xiao Hu, McGahay, Vincent, McGrath, John F, Murray, Conal E, Nayak, Jawahar P, Nguyen, Du B, Rathore, Hazara S, Shaw, Thomas M
Year of Publication 06.12.2005
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Year of Publication 06.12.2005
Patent
Low-leakage n- and p-channel Silicon-gate FET's with an SiO2-Si3N4-gate insulator
Dockerty, R.C., Abbas, S.A., Barile, C.A.
Published in IEEE transactions on electron devices (01.02.1975)
Published in IEEE transactions on electron devices (01.02.1975)
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Journal Article
Stacked via-stud with improved reliability in copper metallurgy
MURRAY CONAL E, BARILE CONRAD A, LANE MICHAEL, RATHORE HAZARA S, DALAL HORMAZDYAR M, LIU XIAO HU, AGARWALA BIRENDRA N, NGUYEN DU B, LEVINE ERNEST, SHAW THOMAS M, ENGLE BRETT H, NAYAK JAWAHAR P, MCGAHAY VINCENT, MCGRATH JOHN F
Year of Publication 06.12.2005
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Year of Publication 06.12.2005
Patent
Stacked via-stud with improved reliability in copper metallurgy
MURRAY CONAL E, ENGEL BRETT H, BARILE CONRAD A, LANE MICHAEL, RATHORE HAZARA S, DALAL HORMAZDYAR M, LIU XIAO HU, AGARWALA BIRENDRA N, NGUYEN DU B, LEVINE ERNEST, SHAW THOMAS M, NAYAK JAWAHAR P, MCGAHAY VINCENT, MCGRATH JOHN F
Year of Publication 27.05.2004
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Year of Publication 27.05.2004
Patent
BIPOLAR TRANSISTOR FABRICATION PROCESS WITH AN ION IMPLANTED EMITTER
GOTH, GEORGE R, NAGARAJAN, ARUNACHALA, RAHEJA, RAJ K, MAKRIS, JAMES S, BARILE, CONRAD A
Year of Publication 04.01.1983
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Year of Publication 04.01.1983
Patent
Bipolar transistor fabrication process with an ion implanted emitter
NAGARAJAN; ARUNACHALA, GOTH; GOERGE R, MAKRIS; JAMES S, BARILE; CONRAD A, RAHEJA; RAJ K
Year of Publication 06.01.1981
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Year of Publication 06.01.1981
Patent