Block-Level Added Redundancy Explicit Authentication for Parallelized Encryption and Integrity Checking of Processor- Memory Transactions
Elbaz, Reouven, Torres, Lionel, Sassatelli, Gilles, Guillemin, Pierre, Bardouillet, Michel, Martinez, Albert
Published in Transactions on Computational Science X (01.01.2010)
Published in Transactions on Computational Science X (01.01.2010)
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Book Chapter
A Comparison of Two Approaches Providing Data Encryption and Authentication on a Processor Memory Bus
Elbaz, Reouven, Torres, Lionel, Sassatelli, Gilles, Guillemin, Pierre, Bardouillet, Michel, Martinez, Albert
Published in Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation (2006)
Published in Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation (2006)
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Book Chapter
Conference Proceeding
A parallelized way to provide data encryption and integrity checking on a processor-memory bus
Elbaz, Reouven, Torres, Lionel, Sassatelli, Gilles, Guillemin, Pierre, Bardouillet, Michel, Martinez, Albert
Published in 2006 43rd ACM/IEEE Design Automation Conference (24.07.2006)
Published in 2006 43rd ACM/IEEE Design Automation Conference (24.07.2006)
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Conference Proceeding
Hardware Engines for Bus Encryption: A Survey of Existing Techniques
Elbaz, R., Torres, L., Sassatelli, G., Guillemin, P., Anguille, C., Bardouillet, M., Buatois, C., Rigaud, J. B.
Published in Design, Automation and Test in Europe (07.03.2005)
Published in Design, Automation and Test in Europe (07.03.2005)
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Conference Proceeding