Strain engineered extremely thin SOI (ETSOI) for high-performance CMOS
Khakifirooz, A., Cheng, K., Nagumo, T., Loubet, N., Adam, T., Reznicek, A., Kuss, J., Shahrjerdi, D., Sreenivasan, R., Ponoth, S., He, H., Kulkarni, P., Liu, Q., Hashemi, P., Khare, P., Luning, S., Mehta, S., Gimbert, J., Zhu, Y., Zhu, Z., Li, J., Madan, A., Levin, T., Monsieur, F., Yamamoto, T., Naczas, S., Schmitz, S., Holmes, S., Aulnette, C., Daval, N., Schwarzenbach, W., Nguyen, B.-Y, Paruchuri, V., Khare, M., Shahidi, G., Doris, B.
Published in 2012 Symposium on VLSI Technology (VLSIT) (01.06.2012)
Published in 2012 Symposium on VLSI Technology (VLSIT) (01.06.2012)
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Conference Proceeding
Dual strained channel CMOS in FDSOI architecture: New insights on the device performance
Le Royer, C., Cassé, M., Cooper, D., Andrieu, F., Weber, O., Brevard, L., Perreau, P., Damlencourt, J.-F., Baudot, S., Prévitali, B., Tabone, C., Allain, F., Scheiblin, P., Rauer, C., Figuet, C., Aulnette, C., Daval, N., Nguyen, B.-Y., Bourdelle, K.K., Gyani, J., Valenza, M.
Published in Solid-state electronics (01.11.2011)
Published in Solid-state electronics (01.11.2011)
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Journal Article
Conference Proceeding
High-Resistivity Substrates with PN Interface Passivation in 22 nm FD-SOI
Rack, M., Nyssens, L., Nabet, M., Schwan, C., Zhao, Z., Lehmann, S., Herrmann, T., Henke, D., Kondrat, A., Soonekindt, C., Koch, F., Kache, T., Kini, D. P., Zimmerhackl, O., Allibert, F., Aulnette, C., Lederer, D., Raskin, J.-P.
Published in 2022 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) (18.04.2022)
Published in 2022 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) (18.04.2022)
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Conference Proceeding
Ultra-thin strained SOI substrate analysis by pseudo-MOS measurements
Gallon, C., Fenouillet-Beranger, C., Bresson, N., Cristoloveanu, S., Allibert, F., Bord, S., Aulnette, C., Delille, D., Latu-Romain, E., Hartmann, J.M., Ernst, T., Andrieu, F., Campidelli, Y., Ghyselen, B., Cayrefourcq, I., Fournel, F., Kernevez, N., Skotnicki, T.
Published in Microelectronic engineering (01.06.2005)
Published in Microelectronic engineering (01.06.2005)
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Journal Article
Conference Proceeding
Dual channel and strain for CMOS co-integration in FDSOI device architecture
Le Royer, C, Casse, M, Andrieu, F, Weber, O, Brevard, L, Perreau, P, Damlencourt, J, Baudot, S, Tabone, C, Allain, F, Scheiblin, P, Rauer, C, Hutin, L, Figuet, C, Aulnette, C, Daval, N, Nguyen, B, Bourdelle, K K
Published in 2010 Proceedings of the European Solid State Device Research Conference (01.09.2010)
Published in 2010 Proceedings of the European Solid State Device Research Conference (01.09.2010)
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Conference Proceeding
Ultra Thin silicon substrate for next generation technology nodes
Schwarzenbach, W, Cauchy, X, Bonnin, O, Boedt, F, Butaud, E, Moulin, C, Kerdiles, S, Gilbert, J.-F, Daval, N, Aulnette, C, Girard, C, Yoshimi, M, Maleville, C
Published in 2010 International Symposium on Semiconductor Manufacturing (ISSM) (01.10.2010)
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Published in 2010 International Symposium on Semiconductor Manufacturing (ISSM) (01.10.2010)
Conference Proceeding
New layer transfers obtained by the SmartCut process
MORICEAU, H, FOURNEL, F, SOUBIE, A, BIASSE, B, SOUSBIE, N, SARTORI, S, MICHAUD, J. F, LETERTRE, F, RAYSSAC, O, CAYREFOURCQ, I, RICHTARCH, C, DAVAL, N, ASPAR, B, AULNETTE, C, AKATSU, T, OSTERNAUD, B, GHYSELEN, B, MAZURE, C, BATAILLOU, B, BEAUMONT, A, MORALES, C, CARTIER, A. M, POCAS, S, LAGAHE, C, JALAGUIER, E
Published in Journal of electronic materials (01.08.2003)
Published in Journal of electronic materials (01.08.2003)
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Conference Proceeding
Journal Article
Strain characterization of strained silicon on insulator wafers
Paillard, V, Ghyselen, B, Aulnette, C, Osternaud, B, Daval, N, Fournel, F, Moriceau, H, Ernst, T, Hartmann, J.M, Lagahe-Blanchard, C, Pocas, S, Leduc, P, Vincent, L, Cristiano, F, Campidelli, Y, Kermarrec, O, Besson, P, Morand, Y
Published in Microelectronic engineering (01.04.2004)
Published in Microelectronic engineering (01.04.2004)
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Journal Article
Conference Proceeding
High-resistivity with PN interface passivation in 22 nm FD-SOI technology for low-loss passives at RF and millimeter-wave frequencies
Nyssens, L., Rack, M., Nabet, M., Schwan, C., Zhao, Z., Lehmann, S., Herrmann, T., Henke, D., Kondrat, A., Soonekindt, C., Koch, F., Kache, T., Kini, D.P., Zimmerhackl, O., Allibert, F., Aulnette, C., Lederer, D., Raskin, J.-P.
Published in Solid-state electronics (01.07.2023)
Published in Solid-state electronics (01.07.2023)
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Journal Article
Modeling and direct extraction of band offset induced by stress engineering in silicon-on-insulator metal-oxide-semiconductor field effect transistors: Implications for device reliability
Garros, X., Rochette, F., Andrieu, F., Baudot, S., Reimbold, G., Aulnette, C., Daval, N., Boulanger, F.
Published in Journal of applied physics (01.06.2009)
Published in Journal of applied physics (01.06.2009)
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Journal Article
Splitting kinetics of Si0.8Ge0.2 layers implanted with H or sequentially with He and H
Nguyen, Phuong, Bourdelle, K. K., Aulnette, C., Lallement, F., Daix, N., Daval, N., Cayrefourcq, I., Letertre, F., Mazuré, C., Bogumilowicz, Y., Tauzin, A., Deguet, C., Cherkashin, N., Claverie, A.
Published in Journal of applied physics (01.12.2008)
Published in Journal of applied physics (01.12.2008)
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Journal Article
Splitting kinetics of Si$_{0.8}$Ge$_{0.2}$ layers implanted with H or sequentially with He and H
Nguyen, P., Bourdelle, K.K., Aulnette, C., Lallement, F., Daix, N., Daval, N., Cayrefourcq, I., Letertre, F., Mazuré, C., Bogumilowicz, Y., Tauzin, A., Deguet, C., Cherkashin, Nikolay, Claverie, Alain
Published in Journal of applied physics (2008)
Published in Journal of applied physics (2008)
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Journal Article
Splitting kinetics of Si 0.8 Ge 0.2 layers implanted with H or sequentially with He and H
Nguyen, Phuong, Bourdelle, K. K., Aulnette, C., Lallement, F., Daix, N., Daval, N., Cayrefourcq, I., Letertre, F., Mazuré, C., Bogumilowicz, Y., Tauzin, A., Deguet, C., Cherkashin, N., Claverie, A.
Published in Journal of applied physics (09.12.2008)
Published in Journal of applied physics (09.12.2008)
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Journal Article
SiGe and Ge on Insulator Wafers
Daval, Nicolas, Figuet, Christophe, Aulnette, Cécile, Landru, Didier, Drazek, Charlotte, Bourdelle, Konstantin K., Guiot, Eric, Letertre, Fabrice, Nguyen, Bich-Yen, Mazure, Carlos
Published in ECS transactions (01.01.2011)
Published in ECS transactions (01.01.2011)
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Journal Article
Ultra-thin SOI for 20nm node and beyond
Aulnette, C., Schwarzenbach, W., Daval, N., Bonnin, O., Nguyen, B-Y, Mazure, C., Maleville, C., Cheng, K., Ponoth, S., Khakifirooz, A., Hook, T., Doris, B.
Published in IEEE 2011 International SOI Conference (01.10.2011)
Published in IEEE 2011 International SOI Conference (01.10.2011)
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Conference Proceeding
PN Junctions Interface Passivation in 22 nm FDSOI for Low-Loss Passives
Nyssens, L., Rack, M., Nabet, M., Schwan, C., Zhao, Z., Lehmann, S., Herrmann, T., Henke, D., Kondrat, A., Soonekindt, C., Koch, F., Kache, T., Kini, D. P., Zimmerhackl, O., Allibert, F., Aulnette, C., Lederer, D., Raskin, J.-P.
Published in 2022 24th International Microwave and Radar Conference (MIKON) (12.09.2022)
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Published in 2022 24th International Microwave and Radar Conference (MIKON) (12.09.2022)
Conference Proceeding
Highly-Strained Silicon-On-Insulator Development
Akatsu, Takeshi, Hartmann, Jean-Michel, Aulnette, Cécile, Le Vaillant, Yves-Matthieu, Rouchon, Denis, Abbadie, Alexandra, Bogumilowicz, Yann, Portigliatti, Lionel, Colnat, Cyrille, Boudou, Nicolas, Lallement, Fabrice, Triolet, Fanny, Figuet, Christophe, Martinez, Muriel, Nguyen, Phuong, Delattre, Cécile, Tsyganenko, Kira, Berne, Cécile, Allibert, Frédéric, Deguet, Chrystel
Published in ECS transactions (20.10.2006)
Published in ECS transactions (20.10.2006)
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Journal Article
Ultra-thin strained SOI substrate analysis by pseudo-MOS measurements
Gallon, C., Fenouillet-Beranger, C., Bresson, N., Cristoloveanu, Sorin, Allibert, Michel, Bord, S., Aulnette, C., Delille, Dominique, Latu-Romain, Eddy, Hartmann, Jean-Michel, Ernst, T., Andrieu, F., Campidelli, Y., Ghyselen, B., Cayrefourcq, I., Fournel, F., Kernevez, N., Skotnicki, T.
Published in Microelectronic engineering (17.06.2005)
Published in Microelectronic engineering (17.06.2005)
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Journal Article
Engineering strained silicon on insulator wafers with the Smart CutTM technology
Ghyselen, B., Hartmann, J.-M., Ernst, T., Aulnette, C., Osternaud, B., Bogumilowicz, Y., Abbadie, A., Besson, P., Rayssac, O., Tiberj, A., Daval, N., Cayrefourq, I., Fournel, F., Moriceau, H., Di Nardo, C., Andrieu, F., Paillard, V., Cabié, M., Vincent, L., Snoeck, E., Cristiano, F., Rocher, A., Ponchet, A., Claverie, A., Boucaud, P., Semeria, M.-N., Bensahel, D., Kernevez, N., Mazure, C.
Published in Solid-state electronics (01.08.2004)
Published in Solid-state electronics (01.08.2004)
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Journal Article