Dramaton: A Near-DRAM Accelerator for Large Number Theoretic Transforms
Park, Yongmo, Pal, Subhankar, Amarnath, Aporva, Swaminathan, Karthik, Lu, Wei D., Buyuktosunoglu, Alper, Bose, Pradip
Published in IEEE computer architecture letters (01.01.2024)
Published in IEEE computer architecture letters (01.01.2024)
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Journal Article
The Celerity Open-Source 511-Core RISC-V Tiered Accelerator Fabric: Fast Architectures and Design Methodologies for Fast Chips
Davidson, Scott, Xie, Shaolin, Torng, Christopher, Al-Hawai, Khalid, Rovinski, Austin, Ajayi, Tutu, Vega, Luis, Zhao, Chun, Zhao, Ritchie, Dai, Steve, Amarnath, Aporva, Veluri, Bandhav, Gao, Paul, Rao, Anuj, Liu, Gai, Gupta, Rajesh K., Zhang, Zhiru, Dreslinski, Ronald, Batten, Christopher, Taylor, Michael Bedford
Published in IEEE MICRO (01.03.2018)
Published in IEEE MICRO (01.03.2018)
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Journal Article
A 7.3 M Output Non-Zeros/J, 11.7 M Output Non-Zeros/GB Reconfigurable Sparse Matrix-Matrix Multiplication Accelerator
Park, Dong-Hyeon, Pal, Subhankar, Feng, Siying, Gao, Paul, Tan, Jielun, Rovinski, Austin, Xie, Shaolin, Zhao, Chun, Amarnath, Aporva, Wesley, Timothy, Beaumont, Jonathan, Chen, Kuan-Yu, Chakrabarti, Chaitali, Taylor, Michael Bedford, Mudge, Trevor, Blaauw, David, Kim, Hun-Seok, Dreslinski, Ronald G.
Published in IEEE journal of solid-state circuits (01.04.2020)
Published in IEEE journal of solid-state circuits (01.04.2020)
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Journal Article
Heterogeneity-Aware Scheduling on SoCs for Autonomous Vehicles
Amarnath, Aporva, Pal, Subhankar, Kassa, Hiwot Tadese, Vega, Augusto, Buyuktosunoglu, Alper, Franke, Hubertus, Wellman, John-David, Dreslinski, Ronald, Bose, Pradip
Published in IEEE computer architecture letters (01.07.2021)
Published in IEEE computer architecture letters (01.07.2021)
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Journal Article
14.5 A 12nm Linux-SMP-Capable RISC-V SoC with 14 Accelerator Types, Distributed Hardware Power Management and Flexible NoC-Based Data Orchestration
Dos Santos, Maico Cassel, Jia, Tianyu, Zuckerman, Joseph, Cochet, Martin, Giri, Davide, Loscalzo, Erik Jens, Swaminathan, Karthik, Tambe, Thierry, Zhang, Jeff Jun, Buyuktosunoglu, Alper, Chiu, Kuan-Lin, Guglielmo, Giuseppe Di, Mantovani, Paolo, Piccolboni, Luca, Tombesi, Gabriele, Trilla, David, Wellman, John-David, Yang, En-Yu, Amarnath, Aporva, Jing, Ying, Mishra, Bakshree, Park, Joshua, Suresh, Vignesh, Adve, Sarita, Bose, Pradip, Brooks, David, Carloni, Luca P., Shepard, Kenneth L., Wei, Gu-Yeon
Published in 2024 IEEE International Solid-State Circuits Conference (ISSCC) (18.02.2024)
Published in 2024 IEEE International Solid-State Circuits Conference (ISSCC) (18.02.2024)
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Conference Proceeding
Evaluating Celerity: A 16-nm 695 Giga-RISC-V Instructions/s Manycore Processor With Synthesizable PLL
Rovinski, Austin, Veluri, Bandhav, Rao, Anuj, Ajayi, Tutu, Puscar, Julian, Dai, Steve, Zhao, Ritchie, Richmond, Dustin, Zhang, Zhiru, Galton, Ian, Batten, Christopher, Zhao, Chun, Taylor, Michael B., Dreslinski, Ronald G., Al-Hawaj, Khalid, Gao, Paul, Xie, Shaolin, Torng, Christopher, Davidson, Scott, Amarnath, Aporva, Vega, Luis
Published in IEEE solid-state circuits letters (01.12.2019)
Published in IEEE solid-state circuits letters (01.12.2019)
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Journal Article
A Neuro-Symbolic Approach to Multi-Agent RL for Interpretability and Probabilistic Decision Making
Subramanian, Chitra, Liu, Miao, Khan, Naweed, Lenchner, Jonathan, Aporva Amarnath, Swaminathan, Sarathkrishna, Riegel, Ryan, Gray, Alexander
Published in arXiv.org (21.02.2024)
Published in arXiv.org (21.02.2024)
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Paper
Journal Article
HetSched: Quality-of-Mission Aware Scheduling for Autonomous Vehicle SoCs
Aporva Amarnath, Pal, Subhankar, Kassa, Hiwot, Vega, Augusto, Alper Buyuktosunoglu, Franke, Hubertus, John-David Wellman, Dreslinski, Ronald, Bose, Pradip
Published in arXiv.org (25.03.2022)
Published in arXiv.org (25.03.2022)
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Journal Article
OuterSPACE: An Outer Product Based Sparse Matrix Multiplication Accelerator
Pal, Subhankar, Beaumont, Jonathan, Park, Dong-Hyeon, Amarnath, Aporva, Feng, Siying, Chakrabarti, Chaitali, Kim, Hun-Seok, Blaauw, David, Mudge, Trevor, Dreslinski, Ronald
Published in 2018 IEEE International Symposium on High Performance Computer Architecture (HPCA) (01.02.2018)
Published in 2018 IEEE International Symposium on High Performance Computer Architecture (HPCA) (01.02.2018)
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Conference Proceeding
STOMP: A Tool for Evaluation of Scheduling Policies in Heterogeneous Multi-Processors
Vega, Augusto, Aporva Amarnath, John-David Wellman, Kassa, Hiwot, Pal, Subhankar, Franke, Hubertus, Alper Buyuktosunoglu, Dreslinski, Ronald, Bose, Pradip
Published in arXiv.org (28.07.2020)
Published in arXiv.org (28.07.2020)
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Paper
Journal Article
R2D3: A Reliability Engine for 3D Parallel Systems
Bagherzadeh, Javad, Amarnath, Aporva, Tan, Jielun, Pal, Subhankar, Dreslinski, Ronald G.
Published in 2020 57th ACM/IEEE Design Automation Conference (DAC) (01.07.2020)
Published in 2020 57th ACM/IEEE Design Automation Conference (DAC) (01.07.2020)
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Conference Proceeding
3DTUBE: A Design Framework for High-Variation Carbon Nanotube-based Transistor Technology
Amarnath, Aporva, Bagherzadeh, Javad, Tan, Jielun, Dreslinski, Ronald G.
Published in 2019 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED) (01.07.2019)
Published in 2019 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED) (01.07.2019)
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Conference Proceeding
A carbon nanotube transistor based RISC-V processor using pass transistor logic
Amarnath, Aporva, Siying Feng, Pal, Subhankar, Ajayi, Tutu, Rovinski, Austin, Dreslinski, Ronald G.
Published in 2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED) (01.07.2017)
Published in 2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED) (01.07.2017)
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Conference Proceeding
A 7.3 M Output Non-Zeros/J Sparse Matrix-Matrix Multiplication Accelerator using Memory Reconfiguration in 40 nm
Pal, Subhankar, Park, Dong-hyeon, Feng, Siying, Gao, Paul, Tan, Jielun, Rovinski, Austin, Xie, Shaolin, Zhao, Chun, Amarnath, Aporva, Wesley, Timothy, Beaumont, Jonathan, Chen, Kuan-Yu, Chakrabarti, Chaitali, Taylor, Michael, Mudge, Trevor, Blaauw, David, Kim, Hun-Seok, Dreslinski, Ronald
Published in 2019 Symposium on VLSI Circuits (01.06.2019)
Published in 2019 Symposium on VLSI Circuits (01.06.2019)
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Conference Proceeding
A 7.3 M Output Non-Zeros/J Sparse Matrix-Matrix Multiplication Accelerator using Memory Reconfiguration in 40 nm
Pal, Subhankar, Park, Dong-hyeon, Feng, Siying, Gao, Paul, Tan, Jielun, Rovinski, Austin, Xie, Shaolin, Zhao, Chun, Amarnath, Aporva, Wesley, Timothy, Beaumont, Jonathan, Chen, Kuan-Yu, Chakrabarti, Chaitali, Taylor, Michael, Mudge, Trevor, Blaauw, David, Kim, Hun-Seok, Dreslinski, Ronald
Published in 2019 Symposium on VLSI Technology (01.06.2019)
Published in 2019 Symposium on VLSI Technology (01.06.2019)
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Conference Proceeding
Learning agent based application scheduling
Franke, Hubertus, Buyuktosunoglu, Alper, Bose, Pradip, Vega, Augusto, Amarnath, Aporva, Wellman, John-David
Year of Publication 23.04.2024
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Year of Publication 23.04.2024
Patent
Heterogeneous system on a chip scheduler with learning agent
Franke, Hubertus, Buyuktosunoglu, Alper, Bose, Pradip, Vega, Augusto, Amarnath, Aporva, Wellman, John-David, Senger, Robert Matthew
Year of Publication 29.08.2023
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Year of Publication 29.08.2023
Patent
Heterogeneous system on a chip scheduler
Franke, Hubertus, Buyuktosunoglu, Alper, Bose, Pradip, Vega, Augusto, Amarnath, Aporva, Wellman, John-David, Senger, Robert Matthew
Year of Publication 18.07.2023
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Year of Publication 18.07.2023
Patent
LEARNING AGENT BASED APPLICATION SCHEDULING
VEGA, Augusto, BUYUKTOSUNOGLU, Alper, FRANKE, Hubertus, WELLMAN, John-David, AMARNATH, Aporva, BOSE, Pradip
Year of Publication 19.01.2023
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Year of Publication 19.01.2023
Patent
A 1.4 GHz 695 Giga Risc-V Inst/s 496-Core Manycore Processor With Mesh On-Chip Network and an All-Digital Synthesized PLL in 16nm CMOS
Rovinski, Austin, Zhao, Chun, Al-Hawaj, Khalid, Gao, Paul, Xie, Shaolin, Torng, Christopher, Davidson, Scott, Amarnath, Aporva, Vega, Luis, Veluri, Bandhav, Rao, Anuj, Ajayi, Tutu, Puscar, Julian, Dai, Steve, Zhao, Ritchie, Richmond, Dustin, Zhang, Zhiru, Galton, Ian, Batten, Christopher, Taylor, Michael B, Dreslinski, Ronald G
Published in 2019 Symposium on VLSI Circuits (01.06.2019)
Published in 2019 Symposium on VLSI Circuits (01.06.2019)
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Conference Proceeding