NSIM: An Interconnection Network Simulator for Extreme-Scale Parallel Computers
MIWA, Hideki, SUSUKITA, Ryutaro, SHIBAMURA, Hidetomo, HIRAO, Tomoya, MAKI, Jun, YOSHIDA, Makoto, KANDO, Takayuki, AJIMA, Yuichiro, MIYOSHI, Ikuo, SHIMIZU, Toshiyuki, OINAGA, Yuji, ANDO, Hisashige, INADOMI, Yuichi, INOUE, Koji, AOYAGI, Mutsumi, MURAKAMI, Kazuaki
Published in IEICE Transactions on Information and Systems (2011)
Published in IEICE Transactions on Information and Systems (2011)
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Journal Article
Validation of hardware error recovery mechanisms for the SPARC64 V microprocessor
Hisashige Ando, Ryuji Kan, Yoshiharu Tosaka, Takahisa, Keiji, Kichiji Hatanaka
Published in 2008 IEEE International Conference on Dependable Systems and Networks With FTCS and DCC (DSN) (01.06.2008)
Published in 2008 IEEE International Conference on Dependable Systems and Networks With FTCS and DCC (DSN) (01.06.2008)
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Conference Proceeding
A Case Study: Energy Efficient High Throughput Chip Multi-Processor Using Reduced-complexity Cores for Transaction Processing Workload
Ando, Hisashige, Asato, Akira, Kawaba, Motoyuki, Okawara, Hideki, Walker, William
Published in Information and Media Technologies (2006)
Published in Information and Media Technologies (2006)
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Journal Article
A 1.3-GHz fifth-generation SPARC64 microprocessor
Ando, H., Yoshida, Y., Inoue, A., Sugiyama, I., Asakawa, T., Morita, K., Muta, T., Motokurumada, T., Okada, S., Yamashita, H., Satsukawa, Y., Konmoto, A., Yamashita, R., Sugiyama, H.
Published in IEEE journal of solid-state circuits (01.11.2003)
Published in IEEE journal of solid-state circuits (01.11.2003)
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Journal Article
NSIM: An Interconnection Network Simulator for Extreme-Scale Parallel Computers : Parallel and Distributed Computing and Networking
MIWA, Hideki, SUSUKITA, Ryutaro, OINAGA, Yuji, ANDO, Hisashige, INADOMI, Yuichi, INOUE, Koji, AOYAGI, Mutsumi, MURAKAMI, Kazuaki, SHIBAMURA, Hidetomo, HIRAO, Tomoya, MAKI, Jun, YOSHIDA, Makoto, KANDO, Takayuki, AJIMA, Yuichiro, MIYOSHI, Ikuo, SHIMIZU, Toshiyuki
Published in IEICE transactions on information and systems (2011)
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Published in IEICE transactions on information and systems (2011)
Journal Article
A 1.3GHz fifth generation SPARC64 microprocessor
Ando, Hisashige, Yoshida, Yuuji, Inoue, Aiichiro, Sugiyama, Itsumi, Asakawa, Takeo, Morita, Kuniki, Muta, Toshiyuki, Motokurumada, Tsuyoshi, Okada, Seishi, Yamashita, Hideo, Satsukawa, Yoshihiko, Konmoto, Akihiko, Yamashita, Ryouichi, Sugiyama, Hiroyuki
Published in Annual ACM IEEE Design Automation Conference: Proceedings of the 40th conference on Design automation; 02-06 June 2003 (02.06.2003)
Published in Annual ACM IEEE Design Automation Conference: Proceedings of the 40th conference on Design automation; 02-06 June 2003 (02.06.2003)
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Conference Proceeding