Dramaton: A Near-DRAM Accelerator for Large Number Theoretic Transforms
Park, Yongmo, Pal, Subhankar, Amarnath, Aporva, Swaminathan, Karthik, Lu, Wei D., Buyuktosunoglu, Alper, Bose, Pradip
Published in IEEE computer architecture letters (01.01.2024)
Published in IEEE computer architecture letters (01.01.2024)
Get full text
Journal Article
The Celerity Open-Source 511-Core RISC-V Tiered Accelerator Fabric: Fast Architectures and Design Methodologies for Fast Chips
Davidson, Scott, Xie, Shaolin, Torng, Christopher, Al-Hawai, Khalid, Rovinski, Austin, Ajayi, Tutu, Vega, Luis, Zhao, Chun, Zhao, Ritchie, Dai, Steve, Amarnath, Aporva, Veluri, Bandhav, Gao, Paul, Rao, Anuj, Liu, Gai, Gupta, Rajesh K., Zhang, Zhiru, Dreslinski, Ronald, Batten, Christopher, Taylor, Michael Bedford
Published in IEEE MICRO (01.03.2018)
Published in IEEE MICRO (01.03.2018)
Get full text
Journal Article
A 7.3 M Output Non-Zeros/J, 11.7 M Output Non-Zeros/GB Reconfigurable Sparse Matrix-Matrix Multiplication Accelerator
Park, Dong-Hyeon, Pal, Subhankar, Feng, Siying, Gao, Paul, Tan, Jielun, Rovinski, Austin, Xie, Shaolin, Zhao, Chun, Amarnath, Aporva, Wesley, Timothy, Beaumont, Jonathan, Chen, Kuan-Yu, Chakrabarti, Chaitali, Taylor, Michael Bedford, Mudge, Trevor, Blaauw, David, Kim, Hun-Seok, Dreslinski, Ronald G.
Published in IEEE journal of solid-state circuits (01.04.2020)
Published in IEEE journal of solid-state circuits (01.04.2020)
Get full text
Journal Article
Heterogeneity-Aware Scheduling on SoCs for Autonomous Vehicles
Amarnath, Aporva, Pal, Subhankar, Kassa, Hiwot Tadese, Vega, Augusto, Buyuktosunoglu, Alper, Franke, Hubertus, Wellman, John-David, Dreslinski, Ronald, Bose, Pradip
Published in IEEE computer architecture letters (01.07.2021)
Published in IEEE computer architecture letters (01.07.2021)
Get full text
Journal Article
14.5 A 12nm Linux-SMP-Capable RISC-V SoC with 14 Accelerator Types, Distributed Hardware Power Management and Flexible NoC-Based Data Orchestration
Dos Santos, Maico Cassel, Jia, Tianyu, Zuckerman, Joseph, Cochet, Martin, Giri, Davide, Loscalzo, Erik Jens, Swaminathan, Karthik, Tambe, Thierry, Zhang, Jeff Jun, Buyuktosunoglu, Alper, Chiu, Kuan-Lin, Guglielmo, Giuseppe Di, Mantovani, Paolo, Piccolboni, Luca, Tombesi, Gabriele, Trilla, David, Wellman, John-David, Yang, En-Yu, Amarnath, Aporva, Jing, Ying, Mishra, Bakshree, Park, Joshua, Suresh, Vignesh, Adve, Sarita, Bose, Pradip, Brooks, David, Carloni, Luca P., Shepard, Kenneth L., Wei, Gu-Yeon
Published in 2024 IEEE International Solid-State Circuits Conference (ISSCC) (18.02.2024)
Published in 2024 IEEE International Solid-State Circuits Conference (ISSCC) (18.02.2024)
Get full text
Conference Proceeding
Evaluating Celerity: A 16-nm 695 Giga-RISC-V Instructions/s Manycore Processor With Synthesizable PLL
Rovinski, Austin, Veluri, Bandhav, Rao, Anuj, Ajayi, Tutu, Puscar, Julian, Dai, Steve, Zhao, Ritchie, Richmond, Dustin, Zhang, Zhiru, Galton, Ian, Batten, Christopher, Zhao, Chun, Taylor, Michael B., Dreslinski, Ronald G., Al-Hawaj, Khalid, Gao, Paul, Xie, Shaolin, Torng, Christopher, Davidson, Scott, Amarnath, Aporva, Vega, Luis
Published in IEEE solid-state circuits letters (01.12.2019)
Published in IEEE solid-state circuits letters (01.12.2019)
Get full text
Journal Article
OuterSPACE: An Outer Product Based Sparse Matrix Multiplication Accelerator
Pal, Subhankar, Beaumont, Jonathan, Park, Dong-Hyeon, Amarnath, Aporva, Feng, Siying, Chakrabarti, Chaitali, Kim, Hun-Seok, Blaauw, David, Mudge, Trevor, Dreslinski, Ronald
Published in 2018 IEEE International Symposium on High Performance Computer Architecture (HPCA) (01.02.2018)
Published in 2018 IEEE International Symposium on High Performance Computer Architecture (HPCA) (01.02.2018)
Get full text
Conference Proceeding
R2D3: A Reliability Engine for 3D Parallel Systems
Bagherzadeh, Javad, Amarnath, Aporva, Tan, Jielun, Pal, Subhankar, Dreslinski, Ronald G.
Published in 2020 57th ACM/IEEE Design Automation Conference (DAC) (01.07.2020)
Published in 2020 57th ACM/IEEE Design Automation Conference (DAC) (01.07.2020)
Get full text
Conference Proceeding
3DTUBE: A Design Framework for High-Variation Carbon Nanotube-based Transistor Technology
Amarnath, Aporva, Bagherzadeh, Javad, Tan, Jielun, Dreslinski, Ronald G.
Published in 2019 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED) (01.07.2019)
Published in 2019 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED) (01.07.2019)
Get full text
Conference Proceeding
A carbon nanotube transistor based RISC-V processor using pass transistor logic
Amarnath, Aporva, Siying Feng, Pal, Subhankar, Ajayi, Tutu, Rovinski, Austin, Dreslinski, Ronald G.
Published in 2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED) (01.07.2017)
Published in 2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED) (01.07.2017)
Get full text
Conference Proceeding
A 7.3 M Output Non-Zeros/J Sparse Matrix-Matrix Multiplication Accelerator using Memory Reconfiguration in 40 nm
Pal, Subhankar, Park, Dong-hyeon, Feng, Siying, Gao, Paul, Tan, Jielun, Rovinski, Austin, Xie, Shaolin, Zhao, Chun, Amarnath, Aporva, Wesley, Timothy, Beaumont, Jonathan, Chen, Kuan-Yu, Chakrabarti, Chaitali, Taylor, Michael, Mudge, Trevor, Blaauw, David, Kim, Hun-Seok, Dreslinski, Ronald
Published in 2019 Symposium on VLSI Circuits (01.06.2019)
Published in 2019 Symposium on VLSI Circuits (01.06.2019)
Get full text
Conference Proceeding
A 7.3 M Output Non-Zeros/J Sparse Matrix-Matrix Multiplication Accelerator using Memory Reconfiguration in 40 nm
Pal, Subhankar, Park, Dong-hyeon, Feng, Siying, Gao, Paul, Tan, Jielun, Rovinski, Austin, Xie, Shaolin, Zhao, Chun, Amarnath, Aporva, Wesley, Timothy, Beaumont, Jonathan, Chen, Kuan-Yu, Chakrabarti, Chaitali, Taylor, Michael, Mudge, Trevor, Blaauw, David, Kim, Hun-Seok, Dreslinski, Ronald
Published in 2019 Symposium on VLSI Technology (01.06.2019)
Published in 2019 Symposium on VLSI Technology (01.06.2019)
Get full text
Conference Proceeding
Unlocking Real-Time Fluorescence Lifetime Imaging: Multi-Pixel Parallelism for FPGA-Accelerated Processing
Erbas, Ismail, Amarnath, Aporva, Pandey, Vikas, Swaminathan, Karthik, Wang, Naigang, Intes, Xavier
Year of Publication 09.10.2024
Year of Publication 09.10.2024
Get full text
Journal Article
Compressing Recurrent Neural Networks for FPGA-accelerated Implementation in Fluorescence Lifetime Imaging
Erbas, Ismail, Pandey, Vikas, Amarnath, Aporva, Wang, Naigang, Swaminathan, Karthik, Radev, Stefan T, Intes, Xavier
Year of Publication 01.10.2024
Year of Publication 01.10.2024
Get full text
Journal Article
A Neuro-Symbolic Approach to Multi-Agent RL for Interpretability and Probabilistic Decision Making
Subramanian, Chitra, Liu, Miao, Khan, Naweed, Lenchner, Jonathan, Amarnath, Aporva, Swaminathan, Sarathkrishna, Riegel, Ryan, Gray, Alexander
Year of Publication 20.02.2024
Year of Publication 20.02.2024
Get full text
Journal Article
HetSched: Quality-of-Mission Aware Scheduling for Autonomous Vehicle SoCs
Amarnath, Aporva, Pal, Subhankar, Kassa, Hiwot, Vega, Augusto, Buyuktosunoglu, Alper, Franke, Hubertus, Wellman, John-David, Dreslinski, Ronald, Bose, Pradip
Year of Publication 24.03.2022
Year of Publication 24.03.2022
Get full text
Journal Article
Learning agent based application scheduling
Franke, Hubertus, Buyuktosunoglu, Alper, Bose, Pradip, Vega, Augusto, Amarnath, Aporva, Wellman, John-David
Year of Publication 23.04.2024
Get full text
Year of Publication 23.04.2024
Patent