Power Optimization of a 0.5V 0.286-to-18MHz ADPLL in 65nm CMOS Process
Galapon, Fredrick Angelo R., Agaton, Mark Allen D.C., Leynes, Arcel G., Noveno, Lemuel Neil M., Alvarez, Anastacia B., Densing, Chris Vincent J., Hizon, John Richard E., Rosales, Marc D., de Leon, Maria Theresa G., Maestro, Rico Jossel M.
Published in 2018 New Generation of CAS (NGCAS) (01.11.2018)
Published in 2018 New Generation of CAS (NGCAS) (01.11.2018)
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