Search Results - "ARVIND HALLIYAL" :: K.UTB vyhledávací portál | TBU Library Retrieval Portal

Low-Temperature Synthesis, Characterization, and Properties of Lead-Based Ferroelectric Niobates

Low-Temperature Synthesis, Characterization, and Properties of Lead-Based Ferroelectric Niobates

by Sekar, Michael M. A., Halliyal, Arvind
Published in Journal of the American Ceramic Society (01.02.1998)

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Journal Article

Metal oxide-polymer thermistors

Metal oxide-polymer thermistors

by MOFFATT, D. M, RUNT, J. P, ARVIND HALLIYAL, NEWNHAM, R. E
Published in Journal of materials science (01.02.1989)

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Journal Article

Optical Analyses (SE and ATR) and Other Properties of LPCVD Si[sub 3]N[sub 4] Thin Films

Optical Analyses (SE and ATR) and Other Properties of LPCVD Si[sub 3]N[sub 4] Thin Films

by Wu, Yun, Zhong, Huicai, Romero, Jeremias, Tabery, Cyrus, Cheung, Cristina, MacDonald, Brian, Bhakta, Jay, Halliyal, Arvind, Cheung, Fred, Ogle, Robert
Published in Journal of the Electrochemical Society (2003)

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Journal Article

Optical analyses (SE and ATR) and other properties of LPCVD Si3N4 thin films

Optical analyses (SE and ATR) and other properties of LPCVD Si3N4 thin films

by YUN WU, HUICAI ZHONG, ROMERO, Jeremias, TABERY, Cyrus, CHEUNG, Cristina, MACDONALD, Brian, BHAKTA, Jay, HALLIYAL, Arvind, CHEUNG, Fred, OGLE, Robert
Published in Journal of the Electrochemical Society (01.12.2003)

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Journal Article

SoC level considerations of 3D technology architecture

SoC level considerations of 3D technology architecture

by Kengeri, S., Banna, S., Halliyal, A.
Published in 2013 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) (01.04.2013)

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Conference Proceeding

MONOS DEVICE HAVING BURIED METAL SILICIDE BIT LINE AND MANUFACTURING METHOD THEREOF

MONOS DEVICE HAVING BURIED METAL SILICIDE BIT LINE AND MANUFACTURING METHOD THEREOF

by NGO, MINH, VAN, HALLIYAL, ARVIND, KRIVOKAPIC, ZORAN, TRIPSAS, NICHOLAS, H, RAMSBEY, MARK, T, OGURA, JUSUKE
Year of Publication 12.10.2016

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Patent

Memory devices containing a high-K dielectric layer

Memory devices containing a high-K dielectric layer

by RAMSBEY MARK T, THOMAS JACK F, HALLIYAL ARVIND, ZHENG WEI
Year of Publication 08.04.2014

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Patent

Integrated process for depositing layer of high-K dielectric with in-situ control of K value and thickness of high-K dielectric layer

Integrated process for depositing layer of high-K dielectric with in-situ control of K value and thickness of high-K dielectric layer

by Halliyal, Arvind, Arsania, Farzad
Year of Publication 04.11.2003

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Patent

Integrated process for depositing layer of high-K dielectric with in-situ control of K value and thickness of high-K dielectric layer

Integrated process for depositing layer of high-K dielectric with in-situ control of K value and thickness of high-K dielectric layer

by ARSANIA FARZAD, HALLIYAL ARVIND
Year of Publication 04.11.2003

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Patent

METHOD OF FORMING RELIABLE CU INTERCONNECTS

METHOD OF FORMING RELIABLE CU INTERCONNECTS

by NGO, MINH, VAN, HALLIYAL, ARVIND, PATON, ERIC
Year of Publication 30.09.2009

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Patent

Semiconductor device with metal gate electrode and silicon oxynitride spacer

Semiconductor device with metal gate electrode and silicon oxynitride spacer

by Ngo, Minh, Halliyal, Arvind
Year of Publication 29.05.2003

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Patent

Method of forming flash memory having pre-interpoly dielectric treatment layer

Method of forming flash memory having pre-interpoly dielectric treatment layer

by Ogle, Robert, Halliyal, Arvind
Year of Publication 17.04.2003

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Patent

Laser thermal annealing method for forming semiconductor low-k dielectric layer

Laser thermal annealing method for forming semiconductor low-k dielectric layer

by NGO MINH VAN, HALLIYAL ARVIND
Year of Publication 18.10.2005

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Patent

Laser thermal annealing method for forming semiconductor low-k dielectric layer

Laser thermal annealing method for forming semiconductor low-k dielectric layer

by Halliyal, Arvind, Ngo, Minh Van
Year of Publication 18.10.2005

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Patent

Method for forming an oxynitride spacer for a metal gate electrode using a PECVD process with a silicon-starving atmosphere

Method for forming an oxynitride spacer for a metal gate electrode using a PECVD process with a silicon-starving atmosphere

by NGO MINH VAN, HALLIYAL ARVIND
Year of Publication 09.03.2005

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Patent

Oxidizing pretreatment of ONO layer for flash memory

Oxidizing pretreatment of ONO layer for flash memory

by Ogle, Robert B, Halliyal, Arvind
Year of Publication 22.02.2005

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Patent

Oxidizing pretreatment of ONO layer for flash memory

Oxidizing pretreatment of ONO layer for flash memory

by OGLE ROBERT B, HALLIYAL ARVIND
Year of Publication 22.02.2005

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Patent

METHOD FOR FORMING AN OXYNITRIDE SPACER FOR A METAL GATE ELECTRODE USING A PECVD PROCESS WITH A SILICON-STARVING ATMOSPHERE

METHOD FOR FORMING AN OXYNITRIDE SPACER FOR A METAL GATE ELECTRODE USING A PECVD PROCESS WITH A SILICON-STARVING ATMOSPHERE

by NGO, MINH, VAN, HALLIYAL, ARVIND
Year of Publication 25.08.2004

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Patent

Doped copper interconnects using laser thermal annealing

Doped copper interconnects using laser thermal annealing

by Halliyal, Arvind, Ngo, Minh Van
Year of Publication 04.05.2004

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Patent

Doped copper interconnects using laser thermal annealing

Doped copper interconnects using laser thermal annealing

by NGO MINH VAN, HALLIYAL ARVIND
Year of Publication 04.05.2004

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Patent

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