13.5 A 512Gb 3-bit/Cell 3D Flash Memory on 128-Wordline-Layer with 132MB/s Write Performance Featuring Circuit-Under-Array Technology
Siau, Chang, Kim, Kwang-Ho, Lee, Seungpil, Isobe, Katsuaki, Shibata, Noboru, Verma, Kapil, Ariki, Takuya, Li, Jason, Yuh, Jong, Amarnath, Anirudh, Nguyen, Qui, Kwon, Ohwon, Jeong, Stanley, Li, Heguang, Hsu, Hua-Ling, Tseng, Tai-yuan, Choi, Steve, Darne, Siddhesh, Anantula, Pradeep, Yap, Alex, Chibvongodze, Hardwell, Miwa, Hitoshi, Yamashita, Minoru, Watanabe, Mitsuyuki, Hayashi, Koichiro, Kato, Yosuke, Miwa, Toru, Kang, Jang Yong, Okumura, Masatoshi, Ookuma, Naoki, Balaga, Muralikrishna, Ramachandra, Venky, Matsuda, Aki, Kulkani, Swaroop, Rachineni, Raghavendra, Manjunath, Pai K., Takehara, Masahito, Pai, Anil, Rajendra, Srinivas, Hisada, Toshiki, Fukuda, Ryo, Tokiwa, Naoya, Kawaguchi, Kazuaki, Yamaoka, Masashi, Komai, Hiromitsu, Minamoto, Takatoshi, Unno, Masaki, Ozawa, Susumu, Nakamura, Hiroshi, Hishida, Tomoo, Kajitani, Yasuyuki, Lin, Lei
Published in 2019 IEEE International Solid- State Circuits Conference - (ISSCC) (01.02.2019)
Published in 2019 IEEE International Solid- State Circuits Conference - (ISSCC) (01.02.2019)
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Conference Proceeding
11.1 A 512Gb 3b/cell flash memory on 64-word-line-layer BiCS technology
Yamashita, Ryuji, Magia, Sagar, Higuchi, Tsutomu, Yoneya, Kazuhide, Yamamura, Toshio, Mizukoshi, Hiroyuki, Zaitsu, Shingo, Yamashita, Minoru, Toyama, Shunichi, Kamae, Norihiro, Lee, Juan, Shuo Chen, Jiawei Tao, Mak, William, Xiaohua Zhang, Ying Yu, Utsunomiya, Yuko, Kato, Yosuke, Sakai, Manabu, Matsumoto, Masahide, Chibvongodze, Hardwell, Ookuma, Naoki, Yabe, Hiroki, Taigor, Subodh, Samineni, Rangarao, Kodama, Takuyo, Kamata, Yoshihiko, Namai, Yuzuru, Huynh, Jonathan, Sung-En Wang, Yankang He, Trung Pham, Saraf, Vivek, Petkar, Akshay, Watanabe, Mitsuyuki, Hayashi, Koichiro, Swarnkar, Prashant, Miwa, Hitoshi, Pradhan, Aditya, Dey, Sulagna, Dwibedy, Debasish, Xavier, Thushara, Balaga, Muralikrishna, Agarwal, Samiksha, Kulkarni, Swaroop, Papasaheb, Zameer, Deora, Sahil, Hong, Patrick, Meiling Wei, Balakrishnan, Gopinath, Ariki, Takuya, Verma, Kapil, Chang Siau, Yingda Dong, Ching-Huang Lu, Miwa, Toru, Moogat, Farookh
Published in 2017 IEEE International Solid-State Circuits Conference (ISSCC) (01.02.2017)
Published in 2017 IEEE International Solid-State Circuits Conference (ISSCC) (01.02.2017)
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Conference Proceeding
Word line architecture for three dimensional NAND flash memory
Ariki, Takuya, Miwa, Toru, Ookuma, Naoki, Hayashi, Koichiro, Yabe, Hiroki
Year of Publication 16.11.2021
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Year of Publication 16.11.2021
Patent
DIFFERENTIAL DBUS SCHEME FOR LOW-LATENCY RANDOM READ FOR NAND MEMORIES
ARIKI, Takuya, OOKUMA, Naoki, MIWA, Toru, YABE, Hiroki, HAYASHI, Koichiro
Year of Publication 20.05.2021
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Year of Publication 20.05.2021
Patent
DIFFERENTIAL DBUS SCHEME FOR LOW-LATENCY RANDOM READ FOR NAND MEMORIES
Ariki, Takuya, Miwa, Toru, Ookuma, Naoki, Hayashi, Koichiro, Yabe, Hiroki
Year of Publication 13.05.2021
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Year of Publication 13.05.2021
Patent
WORD LINE ARCHITECTURE FOR THREE DIMENSIONAL NAND FLASH MEMORY
Ariki, Takuya, Miwa, Toru, Ookuma, Naoki, Hayashi, Koichiro, Yabe, Hiroki
Year of Publication 06.05.2021
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Year of Publication 06.05.2021
Patent
Differential dbus scheme for low-latency random read for NAND memories
Ariki, Takuya, Miwa, Toru, Ookuma, Naoki, Hayashi, Koichiro, Yabe, Hiroki
Year of Publication 20.04.2021
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Year of Publication 20.04.2021
Patent