A 65 nm test structure for SRAM device variability and NBTI statistics
Fischer, Thomas, Amirante, Ettore, Huber, Peter, Hofmann, Karl, Ostermayr, Martin, Schmitt-Landsiedel, Doris
Published in Solid-state electronics (01.07.2009)
Published in Solid-state electronics (01.07.2009)
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Journal Article
Conference Proceeding
Analysis of Read Current and Write Trip Voltage Variability From a 1-MB SRAM Test Structure
Fischer, T., Amirante, E., Huber, P., Nirschl, T., Olbrich, A., Ostermayr, M., Schmitt-Landsiedel, D.
Published in IEEE transactions on semiconductor manufacturing (01.11.2008)
Published in IEEE transactions on semiconductor manufacturing (01.11.2008)
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Journal Article
Conference Proceeding
Masking Techniques for Memory Applications
Asthana, Vivek, Vial, Jean-Christophe, Amirante, Ettore, Chong, Yew Keong
Year of Publication 12.09.2024
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Year of Publication 12.09.2024
Patent
A 65nm test structure for the analysis of NBTI induced statistical variation in SRAM transistors
Fischer, T., Amirante, E., Hofmann, K., Ostermayr, M., Huber, P., Schmitt-Landsiedel, D.
Published in ESSDERC 2008 - 38th European Solid-State Device Research Conference (01.09.2008)
Published in ESSDERC 2008 - 38th European Solid-State Device Research Conference (01.09.2008)
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Conference Proceeding
Buried Metal Techniques for Memory Applications
Asthana, Vivek, Amirante, Ettore, Sony, Chong, Yew Keong, Chen, Andy Wangkun
Year of Publication 09.05.2024
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Year of Publication 09.05.2024
Patent
Circuits and Methods for I/O Circuitry TSV Coupling
Asthana, Vivek, Thyagarajan, Sriram, Amirante, Ettore, Chong, Yew Keong, Chen, Andy Wangkun
Year of Publication 21.12.2023
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Year of Publication 21.12.2023
Patent
BITCELL WITH MULTIPLE READ BITLINES
Thyagarajan, Sriram, Amirante, Ettore, Chong, Yew Keong, Chen, Andy Wangkun
Year of Publication 23.09.2021
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Year of Publication 23.09.2021
Patent
BITCELL WITH MULTIPLE READ BITLINES
CHEN, Andy Wangkun, AMIRANTE, Ettore, CHONG, Yew Keong, THYAGARAJAN, Sriram
Year of Publication 22.09.2021
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Year of Publication 22.09.2021
Patent
Buried Power Rail Architecture
Thyagarajan, Sriram, Amirante, Ettore, Sony, Chong, Yew Keong, Chen, Andy Wangkun
Year of Publication 15.09.2022
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Year of Publication 15.09.2022
Patent
Backside power rail architecture
Kulshrestha, Ayush, Thyagarajan, Sriram, Amirante, Ettore, Sony, Chong, Yew Keong, Chen, Andy Wangkun
Year of Publication 13.09.2022
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Year of Publication 13.09.2022
Patent
Buried power rail structure for providing multi-domain power supply for memory device
Kulshrestha, Ayush, Thyagarajan, Sriram, Amirante, Ettore, Sony, Chong, Yew Keong, Chen, Andy Wangkun
Year of Publication 05.07.2022
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Year of Publication 05.07.2022
Patent
Power-Clock Gating in Adiabatic Logic Circuits
Teichmann, Philip, Fischer, Jürgen, Henzler, Stephan, Amirante, Ettore, Schmitt-Landsiedel, Doris
Published in Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation (2005)
Published in Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation (2005)
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Book Chapter
Conference Proceeding
Backside Power Rail Architecture
Kulshrestha, Ayush, N/A, Sony, Thyagarajan, Sriram, Amirante, Ettore, Chong, Yew Keong, Chen, Andy Wangkun
Year of Publication 17.03.2022
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Year of Publication 17.03.2022
Patent
Fast stability analysis of large-scale SRAM arrays and the impact of NBTI degradation
Drapatz, S., Fischer, T., Hofmann, K., Amirante, E., Huber, P., Ostermayr, M., Georgakos, G., Schmitt-Landsiedel, D.
Published in 2009 Proceedings of ESSCIRC (01.09.2009)
Published in 2009 Proceedings of ESSCIRC (01.09.2009)
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Conference Proceeding
Buried Metal Technique for Critical Signal Nets
Kulshrestha, Ayush, Thyagarajan, Sriram, Amirante, Ettore, Sony, Chong, Yew Keong, Chen, Andy Wangkun
Year of Publication 10.03.2022
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Year of Publication 10.03.2022
Patent
Buried metal technique for critical signal nets
Kulshrestha, Ayush, Thyagarajan, Sriram, Amirante, Ettore, Sony, Chong, Yew Keong, Chen, Andy Wangkun
Year of Publication 08.03.2022
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Year of Publication 08.03.2022
Patent