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"AMERASEKERA; E. AJITH"
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"AMERASEKERA; E. AJITH"
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ESD protection for high density drams using triple-well technology
by
AMERASEKERA
,
E
.
AJITH
Year of Publication
11.08.2000
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Improvements in or relating to integrated circuits
by
AMERASEKERA
,
E
.
AJITH
Year of Publication
05.01.2000
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Semiconductor device with protecting means
by
AMERASEKERA
,
E
.
AJITH
Year of Publication
24.11.1999
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ESD protection for high density DRAMs using triple-well technology
by
AMERASEKERA
;
E
.
AJITH
Year of Publication
07.09.1999
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Esd protection for high density drams using triple-well technology
by
AMERASEKERA
,
E
.,
AJITH
Year of Publication
30.03.1999
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Integrated lateral structure for ESD protection in CMOS/BiCMOS technologies
by
AMERASEKERA
;
E
.
AJITH
Year of Publication
08.09.1998
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ESD PROTECTION OF HIGH-DENSITY DRAM USING TRIPLE WELL TEHCHNOLOGY
by
AMERASEKERA E AJITH
Year of Publication
31.03.1998
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Integrated ESD protection circuit using a substrate triggered lateral NPN
by
Amerasekera
,
E
.
Ajith
,
Duvvury, Charvaka
Year of Publication
22.10.2002
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Integrated ESD protection circuit using a substrate triggered lateral NPN
by
AMERASEKERA E
.
AJITH
,
DUVVURY CHARVAKA
Year of Publication
22.10.2002
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Improvements in or relating to integrated circuits
by
AMERASEKERA
,
E
.
AJITH
Year of Publication
04.02.1998
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Semiconductor device with protecting means
by
AMERASEKERA
,
E
.
AJITH
Year of Publication
07.05.1997
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Electrostatic discharge device and method
by
ASHBURN STANTON P
,
GUPTA VIKAS
,
AMERASEKERA E
.
AJITH
Year of Publication
25.11.2008
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Electrostatic discharge device and method
by
Amerasekera
,
E
.
Ajith
,
Gupta, Vikas
,
Ashburn, Stanton P
Year of Publication
25.11.2008
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Integrated ESD protection circuit using a substrate triggered lateral NPN
by
AMERASEKERA
,
E
.
AJITH
,
DUVVURY, CHARVAKA
Year of Publication
01.03.2000
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System and method for electrostatic discharge protection using lateral PNP or PMOS or both for substrate biasing
by
Chen, Zhiliang Julian
,
Vrotsos, Thomas A
,
Amerasekera
,
Ajith E
Year of Publication
29.03.2005
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System and method for electrostatic discharge protection using lateral PNP or PMOS or both for substrate biasing
by
VROTSOS THOMAS A
,
CHEN ZHILIANG JULIAN
,
AMERASEKERA AJITH E
Year of Publication
29.03.2005
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EOS/ESD protection for high density integrated circuits
by
DUVVURY; CHARVAKA
,
RAMASWAMY; SRIDHAR
,
AMERASEKERA
;
E
.
AJITH
Year of Publication
21.03.2000
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System and method for electrostatic discharge protection using lateral PNP or PMOS or both for substrate biasing
by
VROTSOS THOMAS A
,
CHEN ZHILIANG JULIAN
,
AMERASEKERA AJITH E
Year of Publication
11.03.2004
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Cascoded-MOS ESD protection circuits for mixed voltage chips
by
SALEM; RAOUL B
,
AMERASEKERA
;
E
.
AJITH
Year of Publication
27.07.1999
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CASCODE-CONNECTED MOS ESD PROTECTION CIRCUIT FOR MIXED VOLTAGE CHIP
by
RAUL B SAYLAM
,
AMERASEKERA E AJITH
Year of Publication
21.05.1999
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