Search Results - "ALSMEIER JOHANN" :: K.UTB vyhledávací portál | TBU Library Retrieval Portal

THREE DIMENSIONAL NAND STRING MEMORY DEVICES AND METHODS OF FABRICATION THEREOF

THREE DIMENSIONAL NAND STRING MEMORY DEVICES AND METHODS OF FABRICATION THEREOF

by ALSMEIER JOHANN, PACHAMUTHU JAYAVEL, CHIEN HENRY
Year of Publication 21.04.2016

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Patent

SINGLE-SEMICONDUCTOR-LAYER CHANNEL IN A MEMORY OPENING FOR A THREE-DIMENSIONAL NON-VOLATILE MEMORY DEVICE

SINGLE-SEMICONDUCTOR-LAYER CHANNEL IN A MEMORY OPENING FOR A THREE-DIMENSIONAL NON-VOLATILE MEMORY DEVICE

by ALSMEIER JOHANN, RABKIN PETER, PACHAMUTHU JAYAVEL
Year of Publication 21.04.2016

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Patent

METHOD OF MAKING A MULTILEVEL MEMORY STACK STRUCTURE USING A CAVITY CONTAINING A SACRIFICIAL FILL MATERIAL

METHOD OF MAKING A MULTILEVEL MEMORY STACK STRUCTURE USING A CAVITY CONTAINING A SACRIFICIAL FILL MATERIAL

by SHI, Wenguang, LU, Zhenyu, ALSMEIER, Johann, MAO, Daxin, CHIEN, Henry, ZHANG, Tong
Year of Publication 29.01.2020

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Patent

MULTILEVEL MEMORY STACK STRUCTURE AND METHODS OF MANUFACTURING THE SAME

MULTILEVEL MEMORY STACK STRUCTURE AND METHODS OF MANUFACTURING THE SAME

by ALSMEIER JOHANN, PACHAMUTHU JAYAVEL, CHIEN HENRY
Year of Publication 14.04.2016

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Patent

Three-dimensional NAND device containing support pedestal structures for a buried source line and method of making the same

Three-dimensional NAND device containing support pedestal structures for a buried source line and method of making the same

by Zhang Tong, Kai James, Liu Jin, Alsmeier Johann, Zhang Yanli
Year of Publication 13.03.2018

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Patent

METHOD OF MAKING THREE DIMENSIONAL NAND DEVICE WITH CHANNEL CONTACTING CONDUCTIVE SOURCE LINE

METHOD OF MAKING THREE DIMENSIONAL NAND DEVICE WITH CHANNEL CONTACTING CONDUCTIVE SOURCE LINE

by SHOJI, Go, ZHANG, Yanli, DONG, Yingda, ALSMEIER, Johann, YUAN, Jiahui, PACHAMUTHU, Jayavel
Year of Publication 08.01.2020

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Patent

HIGH STACK 3D MEMORY AND METHOD OF MAKING

HIGH STACK 3D MEMORY AND METHOD OF MAKING

by ALSMEIER JOHANN, PACHAMUTHU JAYAVEL, CHIEN HENRY
Year of Publication 24.03.2016

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Patent

Halbleiterspeicherzelle mit einem Graben und einem planaren Auswahltransistor und Verfahren zu ihrer Herstellung

Halbleiterspeicherzelle mit einem Graben und einem planaren Auswahltransistor und Verfahren zu ihrer Herstellung

by ALSMEIER, JOHANN
Year of Publication 08.03.2007

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Patent

Method of Making a Three-Dimensional Memory Array with Etch Stop

Method of Making a Three-Dimensional Memory Array with Etch Stop

by LEE YAO-SHENG, ALSMEIER JOHANN
Year of Publication 27.02.2014

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Patent

Methods for manufacturing ultrathin semiconductor channel three-dimensional memory devices

Methods for manufacturing ultrathin semiconductor channel three-dimensional memory devices

by Rabkin Peter, Higashitani Masaaki, Alsmeier Johann, Pachamuthu Jayavel
Year of Publication 23.01.2018

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Patent

METHOD OF MAKING A THREE-DIMENSIONAL MEMORY ARRAY WITH ETCH STOP

METHOD OF MAKING A THREE-DIMENSIONAL MEMORY ARRAY WITH ETCH STOP

by LEE, YAO-SHENG, ALSMEIER, JOHANN
Year of Publication 20.02.2014

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Patent

ULTRAHIGH DENSITY VERTICAL NAND MEMORY DEVICE & METHOD OF MAKING THEREOF

ULTRAHIGH DENSITY VERTICAL NAND MEMORY DEVICE & METHOD OF MAKING THEREOF

by SAMACHISA GEORGE, ALSMEIER JOHANN
Year of Publication 05.01.2012

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Patent

Crystalline layer stack for forming conductive layers in a three-dimensional memory structure

Crystalline layer stack for forming conductive layers in a three-dimensional memory structure

by Shi Stephen, Alsmeier Johann, Pachamuthu Jayavel, Baenninger Matthias, Chien Henry
Year of Publication 16.01.2018

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Patent

Three-dimensional memory device and method of making the same using concurrent formation of memory openings and contact openings

Three-dimensional memory device and method of making the same using concurrent formation of memory openings and contact openings

by Mushiga, Mitsuteru, Chowdhury, Murshed, Alsmeier, Johann, Zhang, Tong, Otoi, Hisakazu, Yamaguchi, Kensuke, Cui, Zhixin, Kai, James
Year of Publication 26.11.2019

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Patent

NON-VOLATILE MEMORY HAVING 3D ARRAY OF READ/WRITE ELEMENTS WITH VERTICAL BIT LINES AND LATERALLY ALIGNED ACTIVE ELEMENTS AND METHODS THEREOF

NON-VOLATILE MEMORY HAVING 3D ARRAY OF READ/WRITE ELEMENTS WITH VERTICAL BIT LINES AND LATERALLY ALIGNED ACTIVE ELEMENTS AND METHODS THEREOF

by SAMACHISA, GEORGE, ALSMEIER, JOHANN
Year of Publication 15.12.2011

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Patent

MEMORY CELL WITH HIGH-K CHARGE TRAPPING LAYER

MEMORY CELL WITH HIGH-K CHARGE TRAPPING LAYER

by HIGASHITANI, Masaaki, RABKIN, Peter, ALSMEIER, Johann, PACHAMUTHU, Jayavel
Year of Publication 03.01.2018

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Patent

METHOD OF FORMING MEMORY CELL WITH HIGH-K CHARGE TRAPPING LAYER

METHOD OF FORMING MEMORY CELL WITH HIGH-K CHARGE TRAPPING LAYER

by HIGASHITANI, Masaaki, RABKIN, Peter, ALSMEIER, Johann, PACHAMUTHU, Jayavel
Year of Publication 03.01.2018

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Patent

THREE-DIMENSIONAL MEMORY DEVICE HAVING A HETEROSTRUCTURE QUANTUM WELL CHANNEL

THREE-DIMENSIONAL MEMORY DEVICE HAVING A HETEROSTRUCTURE QUANTUM WELL CHANNEL

by HIGASHITANI, Masaaki, RABKIN, Peter, ALSMEIER, Johann, PACHAMUTHU, Jayavel
Year of Publication 03.01.2018

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Patent

Non-Volatile Memory Having 3d Array of Read/Write Elements with Vertical Bit Lines and Laterally Aligned Active Elements and Methods Thereof

Non-Volatile Memory Having 3d Array of Read/Write Elements with Vertical Bit Lines and Laterally Aligned Active Elements and Methods Thereof

by SAMACHISA GEORGE, ALSMEIER JOHANN
Year of Publication 08.12.2011

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Patent

Multilevel memory stack structure and methods of manufacturing the same

Multilevel memory stack structure and methods of manufacturing the same

by ALSMEIER JOHANN, PACHAMUTHU JAYAVEL, CHIEN HENRY
Year of Publication 05.01.2016

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Patent

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