Search Results - "AGNELLO; PAUL D" :: K.UTB vyhledávací portál | TBU Library Retrieval Portal

Process requirements for continued scaling of CMOS—the need and prospects for atomic-level manipulation

Process requirements for continued scaling of CMOS—the need and prospects for atomic-level manipulation

by Agnello, P. D.
Published in IBM journal of research and development (01.03.2002)

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Journal Article

METHOD FOR FABRICATING ABRUPT SOURCE/DRAIN EXTENSIONS WITH CONTROLLABLE GATE ELECTRODE OVERLAP

METHOD FOR FABRICATING ABRUPT SOURCE/DRAIN EXTENSIONS WITH CONTROLLABLE GATE ELECTRODE OVERLAP

by AGNELLO PAUL D, SMEYS PETER I
Year of Publication 16.04.2001

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Patent

RAISED SOURCE/DRAIN SOI TRANSISTOR, AND CMOS DEVICE AND MANUFACTURING METHOD OF CMOS DEVICE USING ULTRA-THIN SOI(SILICON OVER INSULATOR) SUBSTRATE

RAISED SOURCE/DRAIN SOI TRANSISTOR, AND CMOS DEVICE AND MANUFACTURING METHOD OF CMOS DEVICE USING ULTRA-THIN SOI(SILICON OVER INSULATOR) SUBSTRATE

by PARK HEE MYONG, SHAHIDI GHAVAM G, LEE BYOUNG HUN, AGNELLO PAUL D, SCHEPIS DOMINIC J
Year of Publication 14.07.2004

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Patent

DOUBLE POLYSILICON PROCESS FOR PROVIDING SINGLE CHIP HIGH PERFORMANCE LOGIC AND COMPACT EMBEDDED MEMORY STRUCTURE AND RESULTING CHIP STRUCTURE

DOUBLE POLYSILICON PROCESS FOR PROVIDING SINGLE CHIP HIGH PERFORMANCE LOGIC AND COMPACT EMBEDDED MEMORY STRUCTURE AND RESULTING CHIP STRUCTURE

by DIVAKARUNI RAMACHANDRA, SINITSKY DENNIS, AGNELLO PAUL D, CHEN BOMY A, CROWDER SCOTT W, IYER SURBRAMANIAN S
Year of Publication 12.07.2001

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Patent

DOUBLE GATE TRENCH TRANSISTOR

DOUBLE GATE TRENCH TRANSISTOR

by DIVAKARUNI RAMA, JONES ERIN C, BALLANTINE ARNE W, ADKISSON JAMES W, AGNELLO PAUL D, RANKIN JED H
Year of Publication 18.05.2002

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Patent

2 METHOD OF FABRICATING SEMICONDUCTOR SIDE WALL FIN

2 METHOD OF FABRICATING SEMICONDUCTOR SIDE WALL FIN

by NOWAK EDWARD J, DIVAKARUNI RAMA, JONES ERIN C, BALLANTINE ARNE W, ADKISSON JAMES W, AGNELLO PAUL D, RANKIN JED H
Year of Publication 01.05.2002

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Patent

Optimization of silicon technology for the IBM System z9: IBM System z9

Optimization of silicon technology for the IBM System z9: IBM System z9

by POINDEXTER, D. J, STIFFLER, S. R, EDELSTEIN, D. C, KHARE, M, BRONNER, G. B, NAM, H.-J, BUTT, S. A, WU, P. T, AGNELLO, P. D, IVERS, T, NARASIMHA, S, FAURE, T. B, RANKIN, J. H, GROSCH, D. A, KNOX, M. D
Published in IBM journal of research and development (2007)

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Journal Article

Identification of gate electrode discontinuities in submicron CMOS technologies, and effect on circuit performance

Identification of gate electrode discontinuities in submicron CMOS technologies, and effect on circuit performance

by Jenkins, K.A., Burghartz, J.N., Agnello, P.D.
Published in IEEE transactions on electron devices (01.05.1996)

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Journal Article

In-situ etching of InP by a low pressure transient HCI process

In-situ etching of InP by a low pressure transient HCI process

by Agnello, Paul D., Ghandhi, Sorab K.
Published in Journal of crystal growth (1985)

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Journal Article

Preventing cavitation in high aspect ratio dielectric regions of semiconductor device

Preventing cavitation in high aspect ratio dielectric regions of semiconductor device

by Agnello, Paul D, Malik, Rajeev, Muller, K. Paul
Year of Publication 23.03.2010

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Patent

Preventing cavitation in high aspect ratio dielectric regions of semiconductor device

Preventing cavitation in high aspect ratio dielectric regions of semiconductor device

by MULLER K. PAUL, AGNELLO PAUL D, MALIK RAJEEV
Year of Publication 23.03.2010

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Patent

PREVENTING CAVITATION IN HIGH ASPECT RATIO DIELECTRIC REGIONS OF SEMICONDUCTOR DEVICE

PREVENTING CAVITATION IN HIGH ASPECT RATIO DIELECTRIC REGIONS OF SEMICONDUCTOR DEVICE

by MULLER K. PAUL, AGNELLO PAUL D, MALIK RAJEEV
Year of Publication 11.12.2008

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Patent

Preventing cavitation in high aspect ratio dielectric regions of semiconductor device

Preventing cavitation in high aspect ratio dielectric regions of semiconductor device

by Agnello, Paul D, Malik, Rajeev, Muller, K. Paul
Year of Publication 02.12.2008

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Patent

Preventing cavitation in high aspect ratio dielectric regions of semiconductor device

Preventing cavitation in high aspect ratio dielectric regions of semiconductor device

by MULLER K. PAUL, AGNELLO PAUL D, MALIK RAJEEV
Year of Publication 02.12.2008

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Patent

The use of gas monitors to characterize a low-temperature atmospheric-pressure epitaxial system

The use of gas monitors to characterize a low-temperature atmospheric-pressure epitaxial system

by AGNELLO, P. D, SEDGWICK, T. O
Published in Journal of the Electrochemical Society (01.09.1991)

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Journal Article

Relaxed low-defect SGOI for strained SI CMOS applications

Relaxed low-defect SGOI for strained SI CMOS applications

by DENNARD ROBERT H, FOGEL KEITH E, AGNELLO PAUL D, BEDELL STEPHEN W, DOMENICUCCI ANTHONY G, SADANA DEVENDRA K
Year of Publication 24.07.2012

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Patent

Relaxed low-defect SGOI for strained SI CMOS applications

Relaxed low-defect SGOI for strained SI CMOS applications

by Agnello, Paul D, Bedell, Stephen W, Dennard, Robert H, Domenicucci, Anthony G, Fogel, Keith E, Sadana, Devendra K
Year of Publication 24.07.2012

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Patent

A mass spectrometric study of the reaction of triethylindium with arsine gas

A mass spectrometric study of the reaction of triethylindium with arsine gas

by AGNELLO, P. D, GHANDHI, S. K
Published in Journal of the Electrochemical Society (01.06.1988)

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Journal Article

Alkyl exchange effects between triethylindium and trimethylgallium

Alkyl exchange effects between triethylindium and trimethylgallium

by Agnello, Paul D., Ghandhi, Sorab K.
Published in Journal of crystal growth (01.02.1989)

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Journal Article

The composition dependence of GaInAs grown by organometallic epitaxy

The composition dependence of GaInAs grown by organometallic epitaxy

by Agnello, Paul D., Ghandhi, Sorab K.
Published in Journal of crystal growth (01.10.1989)

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Journal Article

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