Search Results - "ABDERREZAK MARZAKI" :: K.UTB vyhledávací portál | TBU Library Retrieval Portal

Bit-erasable embedded Select in Trench Memory (eSTM)

Bit-erasable embedded Select in Trench Memory (eSTM)

by Marzaki, Abderrezak, Melul, Franck, Akbal, Madjid
Year of Publication 09.07.2024

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Patent

PROCESS FOR FABRICATING AN INTEGRATED CIRCUIT COMPRISING A PHASE OF FORMING TRENCHES IN A SUBSTRATE AND CORRESPONDING INTEGRATED CIRCUIT

PROCESS FOR FABRICATING AN INTEGRATED CIRCUIT COMPRISING A PHASE OF FORMING TRENCHES IN A SUBSTRATE AND CORRESPONDING INTEGRATED CIRCUIT

by MARZAKI, Abderrezak, JULIEN, Franck
Year of Publication 22.04.2021

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Patent

Capacitive electronic chip component

Capacitive electronic chip component

by Fornara, Pascal, Marzaki, Abderrezak
Year of Publication 06.04.2021

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Patent

Integrated ultralong time constant time measurement device and fabrication process

Integrated ultralong time constant time measurement device and fabrication process

by Fornara, Pascal, Marzaki, Abderrezak
Year of Publication 02.03.2021

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Patent

METHOD FOR DETECTING A DIFFERENTIAL FAULT ANALYSIS ATTACK AND A THINNING OF THE SUBSTRATE IN AN INTEGRATED CIRCUIT, AND ASSOCIATED INTEGRATED CIRCUIT

METHOD FOR DETECTING A DIFFERENTIAL FAULT ANALYSIS ATTACK AND A THINNING OF THE SUBSTRATE IN AN INTEGRATED CIRCUIT, AND ASSOCIATED INTEGRATED CIRCUIT

by SARAFIANOS, Alexandre, MARZAKI, Abderrezak
Year of Publication 25.02.2021

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Patent

PROCESS FOR FABRICATING MEDIUM-VOLTAGE TRANSISTORS AND CORRESPONDING INTEGRATED CIRCUIT

PROCESS FOR FABRICATING MEDIUM-VOLTAGE TRANSISTORS AND CORRESPONDING INTEGRATED CIRCUIT

by MARZAKI, Abderrezak, JULIEN, Franck
Year of Publication 04.02.2021

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Patent

Circuit intégré comportant au moins un élément capacitif et procédé de fabrication correspondant

Circuit intégré comportant au moins un élément capacitif et procédé de fabrication correspondant

by MARZAKI, Abderrezak
Year of Publication 28.10.2022

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Patent

Integrated circuit comprising at least one capacitive element and corresponding manufacturing method

Integrated circuit comprising at least one capacitive element and corresponding manufacturing method

by MARZAKI ABDERREZAK
Year of Publication 21.10.2022

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Patent

Non-volatile memory device with vertical state transistor and vertical selection transistor

Non-volatile memory device with vertical state transistor and vertical selection transistor

by Delalleau, Julien, Hubert, Quentin, Marzaki, Abderrezak
Year of Publication 26.03.2024

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Patent

Method for detecting a differential fault analysis attack and a thinning of the substrate in an integrated circuit, and associated integrated circuit

Method for detecting a differential fault analysis attack and a thinning of the substrate in an integrated circuit, and associated integrated circuit

by Sarafianos, Alexandre, Marzaki, Abderrezak
Year of Publication 12.01.2021

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Patent

Compact antifuse element and fabrication process

Compact antifuse element and fabrication process

by Fornara, Pascal, Marzaki, Abderrezak
Year of Publication 05.01.2021

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Patent

READ ONLY MEMORY

READ ONLY MEMORY

by Lisart, Mathieu, Marzaki, Abderrezak, Froment, Benoit
Year of Publication 01.02.2024

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Patent

PN JUNCTION

PN JUNCTION

by MARZAKI, Abderrezak, GUIRLEO, Guillaume, CABOUT, Thomas
Year of Publication 23.11.2023

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Patent

Read only memory

Read only memory

by Lisart, Mathieu, Marzaki, Abderrezak, Froment, Benoit
Year of Publication 14.11.2023

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Patent

New Schmitt Trigger with Controllable Hysteresis using Dual Control Gate-Floating Gate Transistor (DCG-FGT)

New Schmitt Trigger with Controllable Hysteresis using Dual Control Gate-Floating Gate Transistor (DCG-FGT)

by Marzaki, Abderrezak, Bidal, V., Laffont, R., Rahajandraibe, W., Portal, J-M., Bouchakour, R.
Published in International journal of reconfigurable and embedded systems (01.03.2013)

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Journal Article

Elément capacitif intégré et procédé de fabrication correspondant

Elément capacitif intégré et procédé de fabrication correspondant

by MARZAKI, Abderrezak
Year of Publication 01.04.2022

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Patent

METHOD OF DETECTING A POSSIBLE THINNING OF A SUBSTRATE OF AN INTEGRATED CIRCUIT VIA THE REAR FACE THEREOF, AND ASSOCIATED DEVICE

METHOD OF DETECTING A POSSIBLE THINNING OF A SUBSTRATE OF AN INTEGRATED CIRCUIT VIA THE REAR FACE THEREOF, AND ASSOCIATED DEVICE

by SARAFIANOS, Alexandre, MARZAKI, Abderrezak
Year of Publication 18.06.2020

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Patent

CO-INTEGRATED VERTICALLY STRUCTURED CAPACITIVE ELEMENT AND FABRICATION PROCESS

CO-INTEGRATED VERTICALLY STRUCTURED CAPACITIVE ELEMENT AND FABRICATION PROCESS

by MARZAKI, Abderrezak, NIEL, Stephan, REGNIER, Arnaud
Year of Publication 13.07.2023

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Patent

CAPACITIVE ELECTRONIC CHIP COMPONENT

CAPACITIVE ELECTRONIC CHIP COMPONENT

by MARZAKI, Abderrezak, FORNARA, Pascal
Year of Publication 09.04.2020

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Patent

Method of detecting a possible thinning of a substrate of an integrated circuit via the rear face thereof, and associated device

Method of detecting a possible thinning of a substrate of an integrated circuit via the rear face thereof, and associated device

by Sarafianos, Alexandre, Marzaki, Abderrezak
Year of Publication 07.04.2020

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Patent

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