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A Circuit Compatible Accurate Compact Model for Ferroelectric-FETs
Ni, Kai, Jerry, Matthew, Smith, Jeffrey A., Datta, Suman
Published in 2018 IEEE Symposium on VLSI Technology (01.06.2018)
Published in 2018 IEEE Symposium on VLSI Technology (01.06.2018)
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The Complementary FET (CFET) for CMOS scaling beyond N3
Ryckaert, J., Schuddinck, P., Weckx, P., Bouche, G., Vincent, B., Smith, J., Sherazi, Y., Mallik, A., Mertens, H., Demuynck, S., Bao, T. Huynh, Veloso, A., Horiguchi, N., Mocuta, A., Mocuta, D., Boemmels, J.
Published in 2018 IEEE Symposium on VLSI Technology (01.06.2018)
Published in 2018 IEEE Symposium on VLSI Technology (01.06.2018)
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A 4M Synapses integrated Analog ReRAM based 66.5 TOPS/W Neural-Network Processor with Cell Current Controlled Writing and Flexible Network Architecture
Mochida, Reiji, Kouno, Kazuyuki, Hayata, Yuriko, Nakayama, Masayoshi, Ono, Takashi, Suwa, Hitoshi, Yasuhara, Ryutaro, Katayama, Koji, Mikawa, Takumi, Gohou, Yasushi
Published in 2018 IEEE Symposium on VLSI Technology (01.06.2018)
Published in 2018 IEEE Symposium on VLSI Technology (01.06.2018)
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A Methodology to Improve Linearity of Analog RRAM for Neuromorphic Computing
Wu, Wei, Wu, Huaqiang, Gao, Bin, Yao, Peng, Zhang, Xiang, Peng, Xiaochen, Yu, Shimeng, Qian, He
Published in 2018 IEEE Symposium on VLSI Technology (01.06.2018)
Published in 2018 IEEE Symposium on VLSI Technology (01.06.2018)
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True 7nm Platform Technology featuring Smallest FinFET and Smallest SRAM cell by EUV, Special Constructs and 3rd Generation Single Diffusion Break
Jeong, W.C., Kwon, D.J., Nam, K.J., Rim, W.J., Jang, M.S., Kim, H.T., Lee, Y.W., Park, J.S., Lee, E.C., Ha, D.W., Park, C.H., Maeda, S., Cho, H.-J., Jung, S.-M., Kang, H.K., Lee, H.J., Lee, K.W., Lee, T.J., Park, D.W., Kim, B.S., Do, J.H., Fukai, T.
Published in 2018 IEEE Symposium on VLSI Technology (01.06.2018)
Published in 2018 IEEE Symposium on VLSI Technology (01.06.2018)
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XNOR-SRAM: In-Memory Computing SRAM Macro for Binary/Ternary Deep Neural Networks
Jiang, Zhewei, Yin, Shihui, Seok, Mingoo, Seo, Jae-sun
Published in 2018 IEEE Symposium on VLSI Technology (01.06.2018)
Published in 2018 IEEE Symposium on VLSI Technology (01.06.2018)
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Embedded STT-MRAM in 28-nm FDSOI Logic Process for Industrial MCU/IoT Application
Lee, Yong Kyu, Song, Yoonjong, Kim, JooChan, Oh, SeChung, Bae, Byoung-Jae, Lee, SangHumn, Lee, JungHyuk, Pi, UngHwan, Seo, Boyoung, Jung, Hyunsung, Lee, Kilho, Shin, HyunChul, Jung, Hyuntaek, Pyo, Mark, Antonyan, Artur, Lee, Daesop, Hwang, Sohee, Jang, Daehyun, Ji, Yongsung, Lee, Seungbae, Lim, Jungman, Koh, Kwan-Hyeob, Hwang, Kihyun, Hong, Hyeongsun, Park, Kichul, Jeong, Gitae, Yoon, Jong Shik, Jung, E.S.
Published in 2018 IEEE Symposium on VLSI Technology (01.06.2018)
Published in 2018 IEEE Symposium on VLSI Technology (01.06.2018)
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Negative Capacitance, n-Channel, Si FinFETs: Bi-directional Sub-60 mV/dec, Negative DIBL, Negative Differential Resistance and Improved Short Channel Effect
Zhou, Hong, Kwon, Daewoong, Sachid, Angada B., Liao, Yuhung, Chatterjee, Korok, Tan, Ava J., Yadav, Ajay K., Hu, Chenming, Salahuddin, Sayeef
Published in 2018 IEEE Symposium on VLSI Technology (01.06.2018)
Published in 2018 IEEE Symposium on VLSI Technology (01.06.2018)
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Power-performance Trade-offs for Lateral NanoSheets on Ultra-Scaled Standard Cells
Bardon, M. Garcia, Sherazi, Y., Jang, D., Yakimets, D., Schuddinck, P., Baert, R., Mertens, H., Mattii, L., Parvais, B., Mocuta, A., Verkest, D.
Published in 2018 IEEE Symposium on VLSI Technology (01.06.2018)
Published in 2018 IEEE Symposium on VLSI Technology (01.06.2018)
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Capacitor-based Cross-point Array for Analog Neural Network with Record Symmetry and Linearity
Li, Y., Kim, S., Sun, X., Solomon, P., Gokmen, T., Tsai, H., Koswatta, S., Ren, Z., Mo, R., Yeh, C. C., Haensch, W., Leobandung, E.
Published in 2018 IEEE Symposium on VLSI Technology (01.06.2018)
Published in 2018 IEEE Symposium on VLSI Technology (01.06.2018)
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Ferroelectric Switching Delay as Cause of Negative Capacitance and the Implications to NCFETs
Obradovic, B., Rakshit, T., Hatcher, R., Kittl, J. A., Rodder, M. S.
Published in 2018 IEEE Symposium on VLSI Technology (01.06.2018)
Published in 2018 IEEE Symposium on VLSI Technology (01.06.2018)
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22-nm FD-SOI Embedded MRAM with Full Solder Reflow Compatibility and Enhanced Magnetic Immunity
Lee, K., Yamane, K., Noh, S., Naik, V. B., Yang, H., Jang, S. H., Kwon, J., Behin-Aein, B., Chao, R., Lim, J. H., S. K., Gan, K. W., Zeng, D., Thiyagarajah, N., Goh, L. C., Liu, B., Toh, E. H., Jung, B., Wee, T. L., Ling, T., Chan, T. H., Chung, N. L., Ting, J. W., Lakshmipathi, S., Son, J. S., Hwang, J., Zhang, L., Low, R., Krishnan, R., Kitamura, T., You, Y. S., Seet, C. S., Cong, H., Shum, D., Wong, J., Woo, S. T., Lam, J., Quek, E., See, A., Siah, S. Y.
Published in 2018 IEEE Symposium on VLSI Technology (01.06.2018)
Published in 2018 IEEE Symposium on VLSI Technology (01.06.2018)
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A low-power and high-speed True Random Number Generator using generated RTN
Brown, James, Gao, Rui, Ji, Zhigang, Chen, Jiezhi, Wu, Jixuan, Zhang, Jianfu, Zhou, Bo, Shi, Qi, Crowford, Jacob, Zhang, Weidong
Published in 2018 IEEE Symposium on VLSI Technology (01.06.2018)
Published in 2018 IEEE Symposium on VLSI Technology (01.06.2018)
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Half-threshold bias Ioff reduction down to nA range of thermally and electrically stable high-performance integrated OTS selector, obtained by Se enrichment and N-doping of thin GeSe layers
Avasarala, Naga Sruti, Donadio, G. L., Witters, T., Opsomer, K., Govoreanu, B., Fantini, A., Clima, S., Oh, H., Kundu, S., Devulder, W., van der Veen, M. H., Van Houdt, J., Heyns, M., Goux, L., Kar, G. S.
Published in 2018 IEEE Symposium on VLSI Technology (01.06.2018)
Published in 2018 IEEE Symposium on VLSI Technology (01.06.2018)
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Te-based binary OTS selectors with excellent selectivity (>105), endurance (>108) and thermal stability (>450°C)
Yoo, Jongmyung, Koo, Yunmo, Chekol, Solomon Amsalu, Park, Jaehyuk, Song, Jeonghwan, Hwang, Hyunsang
Published in 2018 IEEE Symposium on VLSI Technology (01.06.2018)
Published in 2018 IEEE Symposium on VLSI Technology (01.06.2018)
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First Direct Experimental Studies of Hf0.5Zr0.5O2 Ferroelectric Polarization Switching Down to 100-picosecond in Sub-60mV/dec Germanium Ferroelectric Nanowire FETs
Chung, Wonil, Si, Mengwei, Shrestha, Pragya R., Campbell, Jason P., Cheung, Kin P., Ye, Peide D.
Published in 2018 IEEE Symposium on VLSI Technology (01.06.2018)
Published in 2018 IEEE Symposium on VLSI Technology (01.06.2018)
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Response Speed of Negative Capacitance FinFETs
Kwon, Daewoong, Liao, Yu-Hung, Lin, Yen-Kai, Duarte, Juan Pablo, Chatterjee, Korok, Tan, Ava J., Yadav, Ajay K., Hu, Chenming, Krivokapic, Zoran, Salahuddin, Sayeef
Published in 2018 IEEE Symposium on VLSI Technology (01.06.2018)
Published in 2018 IEEE Symposium on VLSI Technology (01.06.2018)
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Enabling CMOS Scaling Towards 3nm and Beyond
Mocuta, A., Weckx, P., Demuynck, S., Radisic, D., Oniki, Y., Ryckaert, J.
Published in 2018 IEEE Symposium on VLSI Technology (01.06.2018)
Published in 2018 IEEE Symposium on VLSI Technology (01.06.2018)
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Nonvolatile Circuits-Devices Interaction for Memory, Logic and Artificial Intelligence
Dou, Chun-Meng, Chen, Wei-Hao, Xue, Cheng-Xin, Lin, Wei-Yu, Lin, Wei-En, Li, Jun-Yi, Lin, Huan-Ting, Chang, Meng-fan
Published in 2018 IEEE Symposium on VLSI Technology (01.06.2018)
Published in 2018 IEEE Symposium on VLSI Technology (01.06.2018)
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Demonstration of Ultra-Low Voltage and Ultra Low Power STT-MRAM designed for compatibility with 0x node embedded LLC applications
Jan, Guenole, Thomas, Luc, Le, Son, Lee, Yuan-Jen, Liu, Huanlong, Zhu, Jian, Iwata-Harms, Jodi, Patel, Sahil, Tong, Ru-Ying, Sundar, Vignesh, Serrano-Guisan, Santiago, Shen, Dongna, He, Renren, Haq, Jesmin, Teng, Zhongjian Jeffrey, Lam, Vinh, Yang, Yi, Wang, Yu-Jen, Zhong, Tom, Fukuzawa, Hideaki, Wang, Po-Kang
Published in 2018 IEEE Symposium on VLSI Technology (01.06.2018)
Published in 2018 IEEE Symposium on VLSI Technology (01.06.2018)
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