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A Novel 3D AND-type NVM Architecture Capable of High-density, Low-power In-Memory Sum-of-Product Computation for Artificial Intelligence Application
Lue, Hang-Ting, Chen, Weichen, Chang, Hung-Sheng, Wang, Keh-Chung, Lu, Chih-Yuan
Published in 2018 IEEE Symposium on VLSI Technology (01.06.2018)
Published in 2018 IEEE Symposium on VLSI Technology (01.06.2018)
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Si/SiGe superlattice I/O finFETs in a vertically-stacked Gate-All-Around horizontal Nanowire Technology
Hellings, G., Mertens, H., Subirats, A., Simoen, E., Schram, T., Ragnarsson, L.-A., Simicic, M., Chen, S.-H., Parvais, B., Boudier, D., Cretu, B., Machillot, J., Pena, V., Sun, S., Yoshida, N., Kim, N., Mocuta, A., Linten, D., Horiguchi, N.
Published in 2018 IEEE Symposium on VLSI Technology (01.06.2018)
Published in 2018 IEEE Symposium on VLSI Technology (01.06.2018)
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Low RA Magnetic Tunnel Junction Arrays in Conjunction with Low Switching Current and High Breakdown Voltage for STT-MRAM at 10 nm and Beyond
Park, C., Lee, H., Ching, C., Ahn, J., Wang, R., Pakala, M., Kang, S. H.
Published in 2018 IEEE Symposium on VLSI Technology (01.06.2018)
Published in 2018 IEEE Symposium on VLSI Technology (01.06.2018)
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A Threshold Switch Augmented Hybrid-FeFET (H-FeFET) with Enhanced Read Distinguishability and Reduced Programming Voltage for Non-Volatile Memory Applications
Jerry, M., Aziz, A., Ni, K., Datta, S., Gupta, S. K., Shukla, N.
Published in 2018 IEEE Symposium on VLSI Technology (01.06.2018)
Published in 2018 IEEE Symposium on VLSI Technology (01.06.2018)
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High Endurance Self-Heating OTS-PCM Pillar Cell for 3D Stackable Memory
Yeh, C. W., Chien, W. C., Bruce, R. L., Cheng, H. Y., Kuo, I. T., Yang, C. H., Ray, A., Miyazoe, H., Kim, W., Carta, F., Lai, E. K., BrightSky, M., Lung, H. L.
Published in 2018 IEEE Symposium on VLSI Technology (01.06.2018)
Published in 2018 IEEE Symposium on VLSI Technology (01.06.2018)
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Space Program Scheme for 3-D NAND Flash Memory Specialized for the TLC Design
Kang, Ho-Jung, Choi, Nagyong, Lee, Dong Hwan, Lee, Tackhwi, Chung, Sungyong, Bae, Jong-Ho, Park, Byung-Gook, Lee, Jong-Ho
Published in 2018 IEEE Symposium on VLSI Technology (01.06.2018)
Published in 2018 IEEE Symposium on VLSI Technology (01.06.2018)
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Neuromorphic Technology Based on Charge Storage Memory Devices
Lee, Sung-Tae, Lim, Suhwan, Choi, Nagyong, Bae, Jong-Ho, Kim, Chul-Heung, Lee, Soochang, Lee, Dong Hwan, Lee, Tackhwi, Chung, Sungyong, Park, Byung-Gook, Lee, Jong-Ho
Published in 2018 IEEE Symposium on VLSI Technology (01.06.2018)
Published in 2018 IEEE Symposium on VLSI Technology (01.06.2018)
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First Experimental Demonstration of Negative Capacitance InGaAs MOSFETs With Hf0.5Zr0.5O2 Ferroelectric Gate Stack
Luc, Q. H., Fan-Chiang, C. C., Huynh, S. H., Huang, P., Do, H. B., Ha, M. T. H., Jin, Y. D., Nguyen, T. A., Zhang, K. Y., Wang, H. C., Lin, Y. K., Lin, Y. C., Hu, C., Iwai, H., Chang, E. Y.
Published in 2018 IEEE Symposium on VLSI Technology (01.06.2018)
Published in 2018 IEEE Symposium on VLSI Technology (01.06.2018)
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InGaAs-on-Insulator MOSFETs Featuring Scaled Logic Devices and Record RF Performance
Zota, C. B., Convertino, C., Deshpande, V., Merkle, T., Sousa, M., Caimi, D., Czomomaz, L.
Published in 2018 IEEE Symposium on VLSI Technology (01.06.2018)
Published in 2018 IEEE Symposium on VLSI Technology (01.06.2018)
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Metal/P-type GeSn Contacts with Specific Contact Resistivity down to 4.4×10−10 Ω-cm2
Wu, Ying, Wang, Wei, Masudy-Panah, Saeid, Li, Yang, Han, Kaizhen, He, Liuhuiquan, Zhang, Zheng, Lei, Dian, Xu, Shengqiang, Kang, Yuye, Gong, Xiao, Yeo, Yee-Chia
Published in 2018 IEEE Symposium on VLSI Technology (01.06.2018)
Published in 2018 IEEE Symposium on VLSI Technology (01.06.2018)
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GeSn p-FinFETs with Sub-10 nm Fin Width Realized on a 200 mm GeSnOI Substrate: Lowest SS of 63 mV/decade, Highest Gm,int of 900 µS/µm, and High-Field µeff of 275 cm2/Vs
Lei, Dian, Han, Kaizhen, Lee, Kwang Hong, Huang, Yi-Chiau, Wang, Wei, Yadav, Sachin, Kumar, Annie, Wu, Ying, Heliu, Huiquan, Xu, Shengqiang, Kang, Yuye, Li, Yang, Kong, Eugene Y.-J., Tan, Chuan Seng, Gong, Xiao
Published in 2018 IEEE Symposium on VLSI Technology (01.06.2018)
Published in 2018 IEEE Symposium on VLSI Technology (01.06.2018)
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An over 120 dB wide-dynamic-range 3.0 μm pixel image sensor with in-pixel capacitor of 41.7 fF/um2 and high reliability enabled by BEOL 3D capacitor process
Takase, M., Isono, S., Tomekawa, Y., Koyanagi, T., Tokuhara, T., Harada, M., Inoue, Y.
Published in 2018 IEEE Symposium on VLSI Technology (01.06.2018)
Published in 2018 IEEE Symposium on VLSI Technology (01.06.2018)
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Hybrid 14nm FinFET - Silicon Photonics Technology for Low-Power Tb/s/mm2 Optical I/O
Rakowski, M., Ban, Y., De Heyn, P., Pantano, N., Snyder, B., Balakrishnan, S., Van Huylenbroeck, S., Bogaerts, L., Demeurisse, C., Inoue, F., Rebibis, K. J., Nolmans, P., Sun, X., Bex, P., Srinivasan, A., De Coster, J., Lardenois, S., Miller, A., Absil, P., Verheyen, P., Velenis, D., Pantouvaki, M., Van Campenhout, J.
Published in 2018 IEEE Symposium on VLSI Technology (01.06.2018)
Published in 2018 IEEE Symposium on VLSI Technology (01.06.2018)
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10μW/cm2-Class High Power Density Planar Si-Nanowire Thermoelectric Energy Harvester Compatible with CMOS-VLSI Technology
Tomita, M., Oba, S., Himeda, Y., Yamato, R., Shima, K., Kumada, T., Xu, M., Takezawa, H., Mesaki, K., Tsuda, K., Hashimoto, S., Zhan, T., Zhang, H., Kamakura, Y., Suzuki, Y., Inokawa, H., Ikeda, H., Matsukawa, T., Matsuki, T., Watanabe, T.
Published in 2018 IEEE Symposium on VLSI Technology (01.06.2018)
Published in 2018 IEEE Symposium on VLSI Technology (01.06.2018)
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Process Optimization of Perpendicular Magnetic Tunnel Junction Arrays for Last-Level Cache beyond 7 nm Node
Xue, Lin, Ching, Chi, Kontos, Alex, Ahn, Jaesoo, Wang, Xiaodong, Whig, Renu, Tseng, Hsin-wei, Howarth, James, Hassan, Sajjad, Chen, Hao, Bangar, Mangesh, Liang, Shurong, Wang, Rongjun, Pakala, Mahendra
Published in 2018 IEEE Symposium on VLSI Technology (01.06.2018)
Published in 2018 IEEE Symposium on VLSI Technology (01.06.2018)
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Novel In-Memory Matrix-Matrix Multiplication with Resistive Cross-Point Arrays
Liao, Yan, Wu, Huaqiang, Wan, Weier, Zhang, Wenqiang, Gao, Bin, Philip Wong, H.-S., Qian, He
Published in 2018 IEEE Symposium on VLSI Technology (01.06.2018)
Published in 2018 IEEE Symposium on VLSI Technology (01.06.2018)
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Nanosecond Laser Anneal for BEOL Performance Boost in Advanced FinFETs
Lee, Rinus T.P., Petrov, N., Kassim, J., Gribelyuk, M., Yang, J., Cao, L., Yeap, K.B., Shen, T., Zainuddin, A. N., Chandrashekar, A., Ray, S., Ramanathan, E., Mahalingam, A. S., Chaudhuri, R., Mody, J., Damjanovic, D., Sun, Z., Sporer, R., Tang, T. J., Liu, H., Liu, J., Krishnan, B.
Published in 2018 IEEE Symposium on VLSI Technology (01.06.2018)
Published in 2018 IEEE Symposium on VLSI Technology (01.06.2018)
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Record 47 mV/dec top-down vertical nanowire InGaAs/GaAsSb tunnel FETs
Alian, Alireza, Kazzi, Salim El, Verhulst, Anne, Milenin, Alexey, Pinna, Nicolo, Ivanov, Tsvetan, Lin, Dennis, Mocuta, Dan, Collaert, Nadine
Published in 2018 IEEE Symposium on VLSI Technology (01.06.2018)
Published in 2018 IEEE Symposium on VLSI Technology (01.06.2018)
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Modeling of FinFET Self-Heating Effects in multiple FinFET Technology Generations with implication for Transistor and Product Reliability
Sagong, H. C., Choi, K., Kim, J., Jeong, T., Choe, M., Shim, H., Kim, W., Park, J., Shin, S., Pae, S.
Published in 2018 IEEE Symposium on VLSI Technology (01.06.2018)
Published in 2018 IEEE Symposium on VLSI Technology (01.06.2018)
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