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SOT-MRAM 300MM Integration for Low Power and Ultrafast Embedded Memories
Garello, K., Yasin, F., Couet, S., Souriau, L., Swerts, J., Rao, S., Van Beek, S., Kim, W., Liu, E., Kundu, S., Tsvetanova, D., Croes, K., Jossart, N., Grimaldi, E., Baumgartner, M., Crotti, D., Fumemont, A., Gambardella, P., Kar, G. S.
Published in 2018 IEEE Symposium on VLSI Circuits (01.06.2018)
Published in 2018 IEEE Symposium on VLSI Circuits (01.06.2018)
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Conference Proceeding
A Scalable Multi- TeraOPS Deep Learning Processor Core for AI Trainina and Inference
Fleischer, Bruce, Shukla, Sunil, Ziegler, Matthew, Silberman, Joel, Jinwook Oh, Srinivasan, Vijavalakshmi, Jungwook Choi, Mueller, Silvia, Agrawal, Ankur, Babinsky, Tina, Nianzheng Cao, Chia-Yu Chen, Chuang, Pierce, Fox, Thomas, Gristede, George, Guillorn, Michael, Haynie, Howard, Klaiber, Michael, Dongsoo Lee, Shih-Hsien Lo, Maier, Gary, Scheuermann, Michael, Venkataramani, Swagath, Vezyrtzis, Christos, Naigang Wang, Fanchieh Yee, Ching Zhou, Pong-Fei Lu, Curran, Brian, Lel Chang, Gopalakrishnan, Kailash
Published in 2018 IEEE Symposium on VLSI Circuits (01.06.2018)
Published in 2018 IEEE Symposium on VLSI Circuits (01.06.2018)
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Conference Proceeding
A Mixed-Signal Binarized Convolutional-Neural-Network Accelerator Integrating Dense Weight Storage and Multiplication for Reduced Data Movement
Valavi, Hossein, Ramadge, Peter J., Nestler, Eric, Verma, Naveen
Published in 2018 IEEE Symposium on VLSI Circuits (01.06.2018)
Published in 2018 IEEE Symposium on VLSI Circuits (01.06.2018)
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Conference Proceeding
Sticker: A 0.41-62.1 TOPS/W 8Bit Neural Network Processor with Multi-Sparsity Compatible Convolution Arrays and Online Tuning Acceleration for Fully Connected Layers
Zhe Yuan, Jinshan Yue, Huanrui Yang, Zhibo Wang, Jinyang Li, Yixiong Yang, Qingwei Guo, Xueqing Li, Meng-Fan Chang, Huazhong Yang, Yongpan Liu
Published in 2018 IEEE Symposium on VLSI Circuits (01.06.2018)
Published in 2018 IEEE Symposium on VLSI Circuits (01.06.2018)
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A 141 UW, 2.46 PJ/Neuron Binarized Convolutional Neural Network Based Self-Learning Speech Recognition Processor in 28NM CMOS
Shouyi Yin, Peng Ouyang, Shixuan Zheng, Dandan Song, Xiudong Li, Leibo Liu, Shaojun Wei
Published in 2018 IEEE Symposium on VLSI Circuits (01.06.2018)
Published in 2018 IEEE Symposium on VLSI Circuits (01.06.2018)
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Conference Proceeding
A 28NM Integrated True Random Number Generator Harvesting Entropy from MRAM
Kaiyuan Yang, Qing Dong, Zhehong Wang, Yi-Chun Shih, Yu-Der Chih, Chang, Jonathan, Blaauw, David, Svlvester, Dennis
Published in 2018 IEEE Symposium on VLSI Circuits (01.06.2018)
Published in 2018 IEEE Symposium on VLSI Circuits (01.06.2018)
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Conference Proceeding
An All-Digital True-Random-Number Generator with Integrated De-correlation and Bias Correction at 3.2-to-86 MB/S, 2.58 PJ/Bit in 65-NM CMOS
Pamula, V. Rajesh, Xun Sun, Sung Kim, Ur Rahman, Fahim, Baosen Zhang, Sathe, Visvesh S.
Published in 2018 IEEE Symposium on VLSI Circuits (01.06.2018)
Published in 2018 IEEE Symposium on VLSI Circuits (01.06.2018)
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Conference Proceeding
New Generation Dynamically Reconfigurable Processor Technology for Accelerating Embedded AI Applications
Fujii, Taro, Toi, Takao, Tanaka, Teruhito, Togawa, Katsumi, Kitaoka, Toshiro, Nishino, Kengo, Nakamura, Noritsugu, Nakahara, Hiroki, Motomura, Masato
Published in 2018 IEEE Symposium on VLSI Circuits (01.06.2018)
Published in 2018 IEEE Symposium on VLSI Circuits (01.06.2018)
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Conference Proceeding
A 252 × 144 SPAD Pixel Flash Lidar with 1728 Dual-Clock 48.8 PS TDCs, Integrated Histogramming and 14.9-to-1 Compression in 180NM CMOS Technology
Lindner, Scott, Chao Zhang, Antolovic, Ivan Michel, Wolf, Martin, Charbon, Edoardo
Published in 2018 IEEE Symposium on VLSI Circuits (01.06.2018)
Published in 2018 IEEE Symposium on VLSI Circuits (01.06.2018)
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A 112-GB/S PAM4 Transmitter in 16NM FinFET
KeeHian Tan, Ping-Chuan Chiang, Yipeng Wang, Haibing Zhao, Roldan, Arianne, Hongyuan Zhao, Narang, Nakul, Siok Wei Lim, Carey, Declan, Ambatipudi, Sai Lalith Chaitanya, Upadhyaya, Parag, Frans, Yohan, Chang, Ken
Published in 2018 IEEE Symposium on VLSI Circuits (01.06.2018)
Published in 2018 IEEE Symposium on VLSI Circuits (01.06.2018)
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Conference Proceeding
A 4096-Neuron 1M-Synapse 3.8PJ/SOP Spiking Neural Network with On-Chip STDP Learning and Sparse Weights in 10NM FinFET CMOS
Chen, Gregory K., Kumar, Raghavan, Sumbul, H. Ekin, Knag, Phil C., Krishnamurthy, Ram K.
Published in 2018 IEEE Symposium on VLSI Circuits (01.06.2018)
Published in 2018 IEEE Symposium on VLSI Circuits (01.06.2018)
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Conference Proceeding
A >3GHz ERBW 1.1GS/S 8B Two-Sten SAR ADC with Recursive-Weight DAC
Haiwen Chen, Xiong Zhot, Qiang Yu, Fan Zhang, Qiang Li
Published in 2018 IEEE Symposium on VLSI Circuits (01.06.2018)
Published in 2018 IEEE Symposium on VLSI Circuits (01.06.2018)
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Conference Proceeding
Logic Process Compatible 40NM 16MB, Embedded Perpendicular-MRAM with Hybrid-Resistance Reference, Sub-μA Sensing Resolution, and 17.5NS Read Access Time
Yi-Chun Shih, Chia-Fu Lee, Yen-An Chang, Po-Hao Lee, Hon-Jarn Lin, Yu-Lin Chen, Ku-Feng Lin, Ta-Ching Yeh, Hung-Chang Yu, Chuang, Harry, Yu-Der Chih, Chang, Jonathan
Published in 2018 IEEE Symposium on VLSI Circuits (01.06.2018)
Published in 2018 IEEE Symposium on VLSI Circuits (01.06.2018)
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Conference Proceeding
An Ultra-High Energy-Efficient Reconfigurable Processor for Deep Neural Networks with Binary/Ternary Weights in 28NM CMOS
Shouyi Yin, Peng Ouyang, Jianxun Yang, Tianyi Lu, Xiudong Li, Leibo Liu, Shaojun Wei
Published in 2018 IEEE Symposium on VLSI Circuits (01.06.2018)
Published in 2018 IEEE Symposium on VLSI Circuits (01.06.2018)
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Conference Proceeding
A 112GB/S PAM4 Wireline Receiver Using a 64-Way Time-Interleaved SAR ADC in 16NM FinFET
Hudner, James, Carey, Declan, Casey, Ronan, Hearne, Kay, de Abreu Farias Neto, Pedro Wilson, Chlis, Ilias, Erett, Marc, Chi Fung Poon, Laraba, Asma, Hongtao Zhang, Chaitanya Ambatipudi, Sai Lalith, Mahashin, David, Upadhyaya, Parag, Frans, Yohan, Chang, Ken
Published in 2018 IEEE Symposium on VLSI Circuits (01.06.2018)
Published in 2018 IEEE Symposium on VLSI Circuits (01.06.2018)
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Conference Proceeding
Hardware-Enabled Artificial Intelligence
Dally, William J., Gray, C. Thomas, Poulton, John, Khailany, Brucek, Wilson, John, Dennison, Larry
Published in 2018 IEEE Symposium on VLSI Circuits (01.06.2018)
Published in 2018 IEEE Symposium on VLSI Circuits (01.06.2018)
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Conference Proceeding
Artifact-Tolerant Opamp-Less Delta-Modulated Bidirectional Neuro-Interface
Pazhouhandeh, M. Reza, Kassiri, Hossein, Shoukry, Aly, Wesspapir, Iliya, Carlen, Peter, Genov, Roman
Published in 2018 IEEE Symposium on VLSI Circuits (01.06.2018)
Published in 2018 IEEE Symposium on VLSI Circuits (01.06.2018)
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Conference Proceeding
A 13Bit 5GS/S ADC with Time-Interleaved Chopping Calibration in 16NM FinFET
Vaz, Bruno, Verbruggen, Bob, Erdmann, Christophe, Collins, Diarmuid, Mcgrath, John, Boumaalif, Ali, Cullen, Edward, Walsh, Darragh, Morgado, Alonso, Mesadri, Conrado, Long, Brian, Pathepuram, Rajitha, De La Torre, Ronnie, Manlapat, Alvin, Karyotis, Georgios, Tsaliagos, Dimitris, Lynch, Patrick, Peng Lim, Breathnach, Daire, Farley, Brendan
Published in 2018 IEEE Symposium on VLSI Circuits (01.06.2018)
Published in 2018 IEEE Symposium on VLSI Circuits (01.06.2018)
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Conference Proceeding
2.9TOPS/W Reconfigurable Dense/Sparse Matrix-Multiply Accelerator with Unified INT8/INTI6/FP16 Datapath in 14NM Tri-Gate CMOS
Anders, Mark, Kaul, Himanshu, Mathew, Sanu, Suresh, Vikram, Satpathy, Sudhir, Agarwal, Amit, Hsu, Steven, Krishnamurthy, Ram
Published in 2018 IEEE Symposium on VLSI Circuits (01.06.2018)
Published in 2018 IEEE Symposium on VLSI Circuits (01.06.2018)
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Conference Proceeding