Si tunnel transistors with a novel silicided source and 46mV/dec swing
Kanghoon Jeon, Wei-Yip Loh, Patel, P, Chang Yong Kang, Jungwoo Oh, Bowonder, A, Chanro Park, Park, C S, Smith, C, Majhi, P, Hsing-Huang Tseng, Jammy, R, Liu, Tsu-Jae King, Chenming Hu
Published in 2010 Symposium on VLSI Technology (01.06.2010)
Published in 2010 Symposium on VLSI Technology (01.06.2010)
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A highly scalable 8-layer 3D vertical-gate (VG) TFT NAND Flash using junction-free buried channel BE-SONOS device
Hang-Ting Lue, Tzu-Hsuan Hsu, Yi-Hsuan Hsiao, Hong, S P, Wu, M T, Hsu, F H, Lien, N Z, Szu-Yu Wang, Jung-Yu Hsieh, Ling-Wu Yang, Yang, Tahone, Kuang-Chao Chen, Kuang-Yeu Hsieh, Chih-Yuan Lu
Published in 2010 Symposium on VLSI Technology (01.06.2010)
Published in 2010 Symposium on VLSI Technology (01.06.2010)
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Highly-scalable novel access device based on Mixed Ionic Electronic conduction (MIEC) materials for high density phase change memory (PCM) arrays
Gopalakrishnan, K, Shenoy, R S, Rettner, C T, Virwani, K, Bethune, D S, Shelby, R M, Burr, G W, Kellock, A, King, R S, Nguyen, K, Bowers, A N, Jurich, M, Jackson, B, Friz, A M, Topuria, T, Rice, P M, Kurdi, B N
Published in 2010 Symposium on VLSI Technology (01.06.2010)
Published in 2010 Symposium on VLSI Technology (01.06.2010)
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Low leakage and low variability Ultra-Thin Body and Buried Oxide (UT2B) SOI technology for 20nm low power CMOS and beyond
Andrieu, F, Weber, O, Mazurier, J, Thomas, O, Noel, J.-P, Fenouillet-Béranger, C, Mazellier, J.-P, Perreau, P, Poiroux, T, Morand, Y, Morel, T, Allegret, S, Loup, V, Barnola, S, Martin, F, Damlencourt, J.-F, Servin, I, Cassé, M, Garros, X, Rozeau, O, Jaud, M.-A, Cibrario, G, Cluzel, J, Toffoli, A, Allain, F, Kies, R, Lafond, D, Delaye, V, Tabone, C, Tosti, L, Brévard, L, Gaud, P, Paruchuri, V, Bourdelle, K K, Schwarzenbach, W, Bonnin, O, Nguyen, B.-Y, Doris, B, Bœuf, F, Skotnicki, T, Faynot, O
Published in 2010 Symposium on VLSI Technology (01.06.2010)
Published in 2010 Symposium on VLSI Technology (01.06.2010)
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A multi-level-cell spin-transfer torque memory with series-stacked magnetotunnel junctions
Ishigaki, T, Kawahara, T, Takemura, R, Ono, K, Ito, K, Matsuoka, H, Ohno, H
Published in 2010 Symposium on VLSI Technology (01.06.2010)
Published in 2010 Symposium on VLSI Technology (01.06.2010)
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Direct observation of RTN-induced SRAM failure by accelerated testing and its application to product reliability assessment
Takeuchi, K, Nagumo, T, Takeda, K, Asayama, S, Yokogawa, S, Imai, K, Hayashi, Y
Published in 2010 Symposium on VLSI Technology (01.06.2010)
Published in 2010 Symposium on VLSI Technology (01.06.2010)
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Gate-all-around silicon nanowire 25-stage CMOS ring oscillators with diameter down to 3 nm
Bangsaruntip, S, Majumdar, A, Cohen, G M, Engelmann, S U, Zhang, Y, Guillorn, M, Gignac, L M, Mittal, S, Graham, W S, Joseph, E A, Klaus, D P, Chang, J, Cartier, E A, Sleight, J W
Published in 2010 Symposium on VLSI Technology (01.06.2010)
Published in 2010 Symposium on VLSI Technology (01.06.2010)
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World's first monolithic 3D-FPGA with TFT SRAM over 90nm 9 layer Cu CMOS
Naito, T, Ishida, T, Onoduka, T, Nishigoori, M, Nakayama, T, Ueno, Y, Ishimoto, Y, Suzuki, A, Chung, W, Madurawe, R, Wu, S, Ikeda, S, Oyamatsu, H
Published in 2010 Symposium on VLSI Technology (01.06.2010)
Published in 2010 Symposium on VLSI Technology (01.06.2010)
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Ultra-thin-body and BOX (UTBB) fully depleted (FD) device integration for 22nm node and beyond
Liu, Q, Yagishita, A, Loubet, N, Khakifirooz, A, Kulkarni, P, Yamamoto, T, Cheng, K, Fujiwara, M, Cai, J, Dorman, D, Mehta, S, Khare, P, Yako, K, Zhu, Y, Mignot, S, Kanakasabapathy, S, Monfray, S, Boeuf, F, Koburger, C, Sunamura, H, Ponoth, S, Reznicek, A, Haran, B, Upham, A, Johnson, R, Edge, L F, Kuss, J, Levin, T, Berliner, N, Leobandung, E, Skotnicki, T, Hane, M, Bu, H, Ishimaru, K, Kleemeier, W, Takayanagi, M, Doris, B, Sampson, R
Published in 2010 Symposium on VLSI Technology (01.06.2010)
Published in 2010 Symposium on VLSI Technology (01.06.2010)
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Conference Proceeding
A novel CuxSiyO resistive memory in logic technology with excellent data retention and resistance distribution for embedded applications
Wang, M, Luo, W J, Wang, Y L, Yang, L M, Zhu, W, Zhou, P, Yang, J H, Gong, X G, Lin, Y Y, Huang, R, Song, S, Zhou, Q T, Wu, H M, Wu, J G, Chi, M H
Published in 2010 Symposium on VLSI Technology (01.06.2010)
Published in 2010 Symposium on VLSI Technology (01.06.2010)
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Conference Proceeding
MLC PRAM with SLC write-speed and robust read scheme
Hwang, Y N, Um, C Y, Lee, J H, Wei, C G, Oh, H R, Jeong, G T, Jeong, H S, Kim, C H, Chung, C H
Published in 2010 Symposium on VLSI Technology (01.06.2010)
Published in 2010 Symposium on VLSI Technology (01.06.2010)
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Conference Proceeding
Efficient multi-VT FDSOI technology with UTBOX for low power circuit design
Fenouillet-Beranger, C, Thomas, O, Perreau, P, Noel, J.-P, Bajolet, A, Haendler, S, Tosti, L, Barnola, S, Beneyton, R, Perrot, C, de Buttet, C, Abbate, F, Baron, F, Pernet, B, Campidelli, Y, Pinzelli, L, Gouraud, P, Cassé, M, Borowiak, C, Weber, O, Andrieu, F, Denorme, S, Boeuf, F, Faynot, O, Skotnicki, T, Bourdelle, K K, Nguyen, B Y, Boedt, F
Published in 2010 Symposium on VLSI Technology (01.06.2010)
Published in 2010 Symposium on VLSI Technology (01.06.2010)
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Conference Proceeding
Application of a statistical compact model for Random Telegraph Noise to scaled-SRAM Vmin analysis
Tanizawa, M, Ohbayashi, S, Okagaki, T, Sonoda, K, Eikyu, K, Hirano, Y, Ishikawa, K, Tsuchiya, O, Inoue, Y
Published in 2010 Symposium on VLSI Technology (01.06.2010)
Published in 2010 Symposium on VLSI Technology (01.06.2010)
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Analysis and prospect of local variability of drain current in scaled MOSFETs by a new decomposition method
Tsunomura, T, Kumar, A, Mizutani, T, Lee, C, Nishida, A, Takeuchi, K, Inaba, S, Kamohara, S, Terada, K, Hiramoto, T, Mogami, T
Published in 2010 Symposium on VLSI Technology (01.06.2010)
Published in 2010 Symposium on VLSI Technology (01.06.2010)
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Conference Proceeding
On the gate-stack origin threshold voltage variability in scaled FinFETs and multi-FinFETs
Liu, Y X, Endo, K, O'uchi, S, Kamei, T, Tsukada, J, Yamauchi, H, Ishikawa, Y, Hayashida, T, Sakamoto, K, Matsukawa, T, Ogura, A, Masahara, M
Published in 2010 Symposium on VLSI Technology (01.06.2010)
Published in 2010 Symposium on VLSI Technology (01.06.2010)
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Conference Proceeding
A 32nm low power RF CMOS SOC technology featuring high-k/metal gate
VanDerVoorn, P, Agostinelli, M, Choi, S, Curello, G, Deshpande, H, El-Tanani, M A, Hafez, W, Jalan, U, Janbay, L, Kang, M, Koh, K, Komeyli, K, Lakdawala, H, Lin, J, Lindert, N, Mudanai, S, Park, J, Phoa, K, Rahman, A, Rizk, J, Rockford, L, Sacks, G, Soumyanath, K, Tashiro, H, Taylor, S, Tsai, C, Xu, H, Xu, J, Yang, L, Young, I, Yeh, J, Yip, J, Bai, P, Jan, C
Published in 2010 Symposium on VLSI Technology (01.06.2010)
Published in 2010 Symposium on VLSI Technology (01.06.2010)
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Novel cross-point resistive switching memory with self-formed schottky barrier
Minseok Jo, Dong-jun Seong, Seonghyun Kim, Joonmyoung Lee, Wootae Lee, Ju-Bong Park, Sangsoo Park, Seungjae Jung, Jungho Shin, Daeseok Lee, Hyunsang Hwang
Published in 2010 Symposium on VLSI Technology (01.06.2010)
Published in 2010 Symposium on VLSI Technology (01.06.2010)
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20nm gate length trigate pFETs on strained SGOI for high performance CMOS
Hutin, L, Cassé, M, Le Royer, C, Damlencourt, J.-F, Pouydebasque, A, Xu, C, Tabone, C, Hartmann, J.-M, Carron, V, Grampeix, H, Mazzocchi, V, Truche, R, Weber, O, Batude, P, Garros, X, Clavelier, L, Vinet, M, Faynot, O
Published in 2010 Symposium on VLSI Technology (01.06.2010)
Published in 2010 Symposium on VLSI Technology (01.06.2010)
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