Automatic error diagnosis and correction for RTL designs
Kai-hui Chang, Wagner, I., Bertacco, V., Markov, I.L.
Published in 2007 IEEE International High Level Design Validation and Test Workshop (01.11.2007)
Published in 2007 IEEE International High Level Design Validation and Test Workshop (01.11.2007)
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Conference Proceeding
Coverage-directed test generation through automatic constraint extraction
Guzey, O., Wang, L.-C.
Published in 2007 IEEE International High Level Design Validation and Test Workshop (01.11.2007)
Published in 2007 IEEE International High Level Design Validation and Test Workshop (01.11.2007)
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Conference Proceeding
Reliable network-on-chip based on generalized de Bruijn graph
Hosseinabady, M., Kakoee, M.R., Mathew, J., Pradhan, D.K.
Published in 2007 IEEE International High Level Design Validation and Test Workshop (01.11.2007)
Published in 2007 IEEE International High Level Design Validation and Test Workshop (01.11.2007)
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Conference Proceeding
Functional coverage measurements and results in post-Silicon validation of Core™2 duo family
Bojan, T., Arreola, M.A., Shlomo, E., Shachar, T.
Published in 2007 IEEE International High Level Design Validation and Test Workshop (01.11.2007)
Published in 2007 IEEE International High Level Design Validation and Test Workshop (01.11.2007)
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Conference Proceeding
Model-driven test generation for system level validation
Mathaikutty, D.A., Ahuja, S., Dingankar, A., Shukla, S.
Published in 2007 IEEE International High Level Design Validation and Test Workshop (01.11.2007)
Published in 2007 IEEE International High Level Design Validation and Test Workshop (01.11.2007)
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Conference Proceeding
Automatic buffer sizing for rate-constrained KPN applications on multiprocessor system-on-chip
Eric Cheung, Hsieh, H., Balarin, F.
Published in 2007 IEEE International High Level Design Validation and Test Workshop (01.11.2007)
Published in 2007 IEEE International High Level Design Validation and Test Workshop (01.11.2007)
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Conference Proceeding
Hierarchical cache coherence protocol verification one level at a time through assume guarantee
Xiaofang Chen, Yu Yang, Delisi, M., Gopalakrishnan, G., Ching-Tsun Chou
Published in 2007 IEEE International High Level Design Validation and Test Workshop (01.11.2007)
Published in 2007 IEEE International High Level Design Validation and Test Workshop (01.11.2007)
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Conference Proceeding
Framework for fast and accurate performance simulation of multiprocessor systems
Eric Cheung, Hsieh, H., Balarin, F.
Published in 2007 IEEE International High Level Design Validation and Test Workshop (01.11.2007)
Published in 2007 IEEE International High Level Design Validation and Test Workshop (01.11.2007)
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Conference Proceeding
Automatic generation of functional coverage models from CTL
Verma, S., Harris, I.G., Ramineni, K.
Published in 2007 IEEE International High Level Design Validation and Test Workshop (01.11.2007)
Published in 2007 IEEE International High Level Design Validation and Test Workshop (01.11.2007)
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Conference Proceeding
Bug analysis and corresponding error models in real designs
Tao Lv, Tong Xu, Yang Zhao, Huawei Li, Xiaowei Li
Published in 2007 IEEE International High Level Design Validation and Test Workshop (01.11.2007)
Published in 2007 IEEE International High Level Design Validation and Test Workshop (01.11.2007)
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Conference Proceeding
Intel's Post Silicon functional validation approach
Tommy, B., Igor, F., Robert, M.
Published in 2007 IEEE International High Level Design Validation and Test Workshop (01.11.2007)
Published in 2007 IEEE International High Level Design Validation and Test Workshop (01.11.2007)
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Conference Proceeding
Automatic TLM generation for C-Based MPSoC design
Lo, L.L.C.Y., Abdi, S.
Published in 2007 IEEE International High Level Design Validation and Test Workshop (01.11.2007)
Published in 2007 IEEE International High Level Design Validation and Test Workshop (01.11.2007)
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Conference Proceeding
A novel formal approach to generate high-level test vectors without ILP and SAT solvers
Alizadeh, B., Fujita, M.
Published in 2007 IEEE International High Level Design Validation and Test Workshop (01.11.2007)
Published in 2007 IEEE International High Level Design Validation and Test Workshop (01.11.2007)
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Conference Proceeding
Formal model construction using HDL simulation semantics
Buck, J., Dong Wang, Yunshan Zhu
Published in 2007 IEEE International High Level Design Validation and Test Workshop (01.11.2007)
Published in 2007 IEEE International High Level Design Validation and Test Workshop (01.11.2007)
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Conference Proceeding
AME: an abstract middleware environment for validating networked embedded systems applications
Fummi, F., Perbellini, G., Quaglia, D., Vinco, S.
Published in 2007 IEEE International High Level Design Validation and Test Workshop (01.11.2007)
Published in 2007 IEEE International High Level Design Validation and Test Workshop (01.11.2007)
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Conference Proceeding
Automating the IEEE std. 1500 compliance verification for embedded cores
Benso, A., Di Carlo, S., Prinetto, P., Bosio, A.
Published in 2007 IEEE International High Level Design Validation and Test Workshop (01.11.2007)
Published in 2007 IEEE International High Level Design Validation and Test Workshop (01.11.2007)
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Conference Proceeding
An approach for computing the initial state for retimed synchronous sequential circuits
Chabini, N., Wolf, W.
Published in 2007 IEEE International High Level Design Validation and Test Workshop (01.11.2007)
Published in 2007 IEEE International High Level Design Validation and Test Workshop (01.11.2007)
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Conference Proceeding
Transactors for parallel hardware and software co-design
Asanovic, K.
Published in 2007 IEEE International High Level Design Validation and Test Workshop (01.11.2007)
Published in 2007 IEEE International High Level Design Validation and Test Workshop (01.11.2007)
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Conference Proceeding
Improving feasible interactions among multiple processes
Ramineni, K., Harris, I.G., Verma, S.
Published in 2007 IEEE International High Level Design Validation and Test Workshop (01.11.2007)
Published in 2007 IEEE International High Level Design Validation and Test Workshop (01.11.2007)
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Conference Proceeding