Integrated circuit and design structure having reduced through silicon via-induced stress
Kinsman Brian L, Sprogis Edmund J, Rassel Robert M, Vanslette Daniel S, Goplen Brent A, Bonn Jeffrey P
Year of Publication 02.08.2016
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Year of Publication 02.08.2016
Patent
INTEGRATED CIRCUIT AND DESIGN STRUCTURE HAVING REDUCED THROUGH SILICON VIA-INDUCED STRESS
BONN JEFFREY P, GOPLEN BRENT A, VANSLETTE DANIEL S, KINSMAN BRIAN L, RASSEL ROBERT M, SPROGIS EDMUND J
Year of Publication 19.07.2012
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Year of Publication 19.07.2012
Patent