A Decision-Error-Tolerant 45 nm CMOS 7b 1 GS/s Nonbinary 2b/Cycle SAR ADC
Hyeok-Ki Hong, Wan Kim, Hyun-Wook Kang, Sun-Jae Park, Choi, Michael, Ho-Jin Park, Seung-Tak Ryu
Published in IEEE journal of solid-state circuits (01.02.2015)
Published in IEEE journal of solid-state circuits (01.02.2015)
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Journal Article
A 0.6 V 12 b 10 MS/s Low-Noise Asynchronous SAR-Assisted Time-Interleaved SAR (SATI-SAR) ADC
Kim, Wan, Hong, Hyeok-Ki, Roh, Yi-Ju, Kang, Hyun-Wook, Hwang, Sun-Il, Jo, Dong-Shin, Chang, Dong-Jin, Seo, Min-Jae, Ryu, Seung-Tak
Published in IEEE journal of solid-state circuits (01.08.2016)
Published in IEEE journal of solid-state circuits (01.08.2016)
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Journal Article
A Sign-Equality-Based Background Timing-Mismatch Calibration Algorithm for Time-Interleaved ADCs
Kang, Hyun-Wook, Hong, Hyeok-Ki, Park, Sanghoon, Kim, Ki-Jin, Ahn, Kwang-Ho, Ryu, Seung-Tak
Published in IEEE transactions on circuits and systems. II, Express briefs (01.06.2016)
Published in IEEE transactions on circuits and systems. II, Express briefs (01.06.2016)
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Journal Article
An 8.6 ENOB 900MS/s time-interleaved 2b/cycle SAR ADC with a 1b/cycle reconfiguration for resolution enhancement
Hyeok-Ki Hong, Hyun-Wook Kang, Sung, B., Choong-Hoon Lee, Choi, M., Ho-Jin Park, Seung-Tak Ryu
Published in 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers (01.02.2013)
Published in 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers (01.02.2013)
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Conference Proceeding
A 65 nm 0.08-to-680 MHz Low-Power Synthesizable MDLL With Nested-Delay Cell and Background Static Phase Offset Calibration
Chang, Dong-Jin, Seo, Min-Jae, Hong, Hyeok-Ki, Ryu, Seung-Tak
Published in IEEE transactions on circuits and systems. II, Express briefs (01.03.2018)
Published in IEEE transactions on circuits and systems. II, Express briefs (01.03.2018)
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Journal Article
A 7b 1GS/s 7.2mW nonbinary 2b/cycle SAR ADC with register-to-DAC direct control
Hyeok-Ki Hong, Wan Kim, Sun-Jae Park, Choi, M., Ho-Jin Park, Seung-Tak Ryu
Published in Proceedings of the IEEE 2012 Custom Integrated Circuits Conference (01.09.2012)
Published in Proceedings of the IEEE 2012 Custom Integrated Circuits Conference (01.09.2012)
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Conference Proceeding
3D 3D NANOPROBE DEVICE AND ELECTRONIC DEVICES COMPRISING THE SAME
KIM, SEONG JOONG, BAE, CHI SUNG, KIM, MI KYUNG, HONG, HYEOK KI, KIM, JONG HAN, PARK, KI TAE
Year of Publication 03.06.2024
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Year of Publication 03.06.2024
Patent
A 6 bit 2 GS/s flash-assisted time-interleaved (FATI) SAR ADC with background offset calibration
Ba-Ro-Saim Sung, Chang-Kyo Lee, Wan Kim, Jong-In Kim, Hyeok-Ki Hong, Ghil-Geun Oh, Choong-Hoon Lee, Choi, Michael, Ho-Jin Park, Seung-Tak Ryu
Published in 2013 IEEE Asian Solid-State Circuits Conference (A-SSCC) (01.11.2013)
Published in 2013 IEEE Asian Solid-State Circuits Conference (A-SSCC) (01.11.2013)
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Conference Proceeding