Fabrication and electrical characterization of 5×50um through silicon vias for 3D integration
Bhushan, Bharat, Minrui Yu, Dukovic, John, Wong, Loke Yuen, Kitowski, Aksel, Mun Kvu Park, Hua, John, Bolagond, Shwetha, Chan, Anthony C.-T, Toh, Chin Hock, Sundarrajan, Arvind, Kumar, Niranjan, Ramaswami, Sesh
Published in 2013 IEEE International Interconnect Technology Conference - IITC (01.06.2013)
Published in 2013 IEEE International Interconnect Technology Conference - IITC (01.06.2013)
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