Limited switch dynamic logic circuits for high-speed low-power circuit design
Belluomini, W., Jamsek, D., Martin, A. K., McDowell, C., Montoye, R. K., Ngo, H. C., Sawada, J.
Published in IBM journal of research and development (01.03.2006)
Published in IBM journal of research and development (01.03.2006)
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Journal Article
A decompression core for PowerPC
Kemp, T. M., Montoye, R. K., Harper, J. D., Palmer, J. D., Auerbach, D. J.
Published in IBM journal of research and development (01.11.1998)
Published in IBM journal of research and development (01.11.1998)
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Journal Article
Second-generation RISC floating point with multiply-add fused
Hokenek, E., Montoye, R.K., Cook, P.W.
Published in IEEE journal of solid-state circuits (01.10.1990)
Published in IEEE journal of solid-state circuits (01.10.1990)
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Journal Article
An 8T-SRAM for Variability Tolerance and Low-Voltage Operation in High-Performance Caches
Chang, L., Montoye, R.K., Nakamura, Y., Batson, K.A., Eickemeyer, R.J., Dennard, R.H., Haensch, W., Jamsek, D.
Published in IEEE journal of solid-state circuits (01.04.2008)
Published in IEEE journal of solid-state circuits (01.04.2008)
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Journal Article
Conference Proceeding
A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons
Seo, J., Brezzo, B., Liu, Y., Parker, B. D., Esser, S. K., Montoye, R. K., Rajendran, B., Tierno, J. A., Chang, L., Modha, D. S., Friedman, D. J.
Published in 2011 IEEE Custom Integrated Circuits Conference (CICC) (01.09.2011)
Published in 2011 IEEE Custom Integrated Circuits Conference (CICC) (01.09.2011)
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Conference Proceeding
Matrix-matrix multiplication on a large register file architecture with indirection
Sreedhar, Dheeraj, Derby, J. H., Montoye, R. K., Johnson, C. L.
Published in 2014 21st International Conference on High Performance Computing (HiPC) (01.12.2014)
Published in 2014 21st International Conference on High Performance Computing (HiPC) (01.12.2014)
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Conference Proceeding
Processor architecture for software implementation of multi-sector G-RAKE receivers for HSUPA wireless infrastructure
Sreedhar, D., Derby, J. H., Vega, A. J., Rogers, B., Johnson, C. L., Montoye, R. K.
Published in 2013 IEEE International Conference on Acoustics, Speech and Signal Processing (01.05.2013)
Published in 2013 IEEE International Conference on Acoustics, Speech and Signal Processing (01.05.2013)
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Conference Proceeding
Stable SRAM cell design for the 32 nm node and beyond
Chang, L., Fried, D.M., Hergenrother, J., Sleight, J.W., Dennard, R.H., Montoye, R.K., Sekaric, L., McNab, S.J., Topol, A.W., Adams, C.D., Guarini, K.W., Haensch, W.
Published in Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005 (2005)
Published in Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005 (2005)
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Conference Proceeding
Controlled-load limited switch dynamic logic circuit
Sivagnaname, J., Ngo, H.C., Nowka, K.J., Montoye, R.K., Brown, R.B.
Published in Sixth international symposium on quality electronic design (isqed'05) (2005)
Published in Sixth international symposium on quality electronic design (isqed'05) (2005)
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Conference Proceeding
IBM second-generation RISC machine organization
Bakoglu, H.B., Grohoski, G.F., Thatcher, L.E., Kahle, J.A., Moore, C.R., Tuttle, D.P., Maule, W.E., Hardell, W.R., Hicks, D.A., Nguyenphu, M., Montoye, R.K., Glover, W.T., Dhawan, S.
Published in Proceedings 1989 IEEE International Conference on Computer Design: VLSI in Computers and Processors (1989)
Published in Proceedings 1989 IEEE International Conference on Computer Design: VLSI in Computers and Processors (1989)
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Conference Proceeding