Limited switch dynamic logic circuits for high-speed low-power circuit design
Belluomini, W., Jamsek, D., Martin, A. K., McDowell, C., Montoye, R. K., Ngo, H. C., Sawada, J.
Published in IBM journal of research and development (01.03.2006)
Published in IBM journal of research and development (01.03.2006)
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Journal Article
A decompression core for PowerPC
Kemp, T. M., Montoye, R. K., Harper, J. D., Palmer, J. D., Auerbach, D. J.
Published in IBM journal of research and development (01.11.1998)
Published in IBM journal of research and development (01.11.1998)
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Journal Article
Matrix-matrix multiplication on a large register file architecture with indirection
Sreedhar, Dheeraj, Derby, J. H., Montoye, R. K., Johnson, C. L.
Published in 2014 21st International Conference on High Performance Computing (HiPC) (01.12.2014)
Published in 2014 21st International Conference on High Performance Computing (HiPC) (01.12.2014)
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Conference Proceeding
Stable SRAM cell design for the 32 nm node and beyond
Chang, L., Fried, D.M., Hergenrother, J., Sleight, J.W., Dennard, R.H., Montoye, R.K., Sekaric, L., McNab, S.J., Topol, A.W., Adams, C.D., Guarini, K.W., Haensch, W.
Published in Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005 (2005)
Published in Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005 (2005)
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Conference Proceeding
Controlled-load limited switch dynamic logic circuit
Sivagnaname, J., Ngo, H.C., Nowka, K.J., Montoye, R.K., Brown, R.B.
Published in Sixth international symposium on quality electronic design (isqed'05) (2005)
Published in Sixth international symposium on quality electronic design (isqed'05) (2005)
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Conference Proceeding