Search Results - "JOUPPI, Norman Paul" :: K.UTB vyhledávací portál | TBU Library Retrieval Portal

SPECIAL PURPOSE NEURAL NETWORK TRAINING CHIP

SPECIAL PURPOSE NEURAL NETWORK TRAINING CHIP

by NORRIE THOMAS, PHELPS ANDREW EVERETT, JOUPPI NORMAN PAUL, TEMAM OLIVIER
Year of Publication 30.04.2024

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Patent

PERFORMING MATRIX MULTIPLICATION IN HARDWARE

PERFORMING MATRIX MULTIPLICATION IN HARDWARE

by PHELPS ANDREW EVERETT, JOUPPI NORMAN PAUL
Year of Publication 31.05.2021

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Patent

SPECIAL PURPOSE NEURAL NETWORK TRAINING CHIP

SPECIAL PURPOSE NEURAL NETWORK TRAINING CHIP

by NORRIE THOMAS, PHELPS ANDREW EVERETT, JOUPPI NORMAN PAUL, TEMAM OLIVIER
Year of Publication 05.01.2023

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Patent

MODIFYING MACHINE LEARNING MODELS TO IMPROVE LOCALITY

MODIFYING MACHINE LEARNING MODELS TO IMPROVE LOCALITY

by YOON DOE HYUN, JOUPPI NORMAN PAUL, PATIL NISHANT
Year of Publication 18.11.2022

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Patent

SPECIAL PURPOSE NEURAL NETWORK TRAINING CHIP

SPECIAL PURPOSE NEURAL NETWORK TRAINING CHIP

by NORRIE THOMAS, PHELPS ANDREW EVERETT, JOUPPI NORMAN PAUL, TEMAM OLIVIER
Year of Publication 13.10.2021

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Patent

ADAPTIVE GRANULARITY ROW-BUFFER CACHE

ADAPTIVE GRANULARITY ROW-BUFFER CACHE

by LI SHENG, JOUPPI NORMAN PAUL
Year of Publication 14.10.2015

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Patent

REPRESENTING DATA USING A GROUP OF MULTILEVEL MEMORY CELLS

REPRESENTING DATA USING A GROUP OF MULTILEVEL MEMORY CELLS

by YOON DOE HYUN, MURALIMANOHAR NAVEEN, CHANG JICHUAN, SCHREIBER ROBERT, JOUPPI NORMAN PAUL
Year of Publication 08.01.2016

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Patent

CACHING DATA IN A MEMORY SYSTEM HAVING MEMORY NODES AT DIFFERENT HIERARCHICAL LEVELS

CACHING DATA IN A MEMORY SYSTEM HAVING MEMORY NODES AT DIFFERENT HIERARCHICAL LEVELS

by LI SHENG, CHEN KE, JOUPPI NORMAN PAUL
Year of Publication 25.11.2015

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Patent

LOCAL ERROR DETECTION AND GLOBAL ERROR CORRECTION

LOCAL ERROR DETECTION AND GLOBAL ERROR CORRECTION

by MURALIMANOHAR NAVEEN, DAVIS ALAN LYNN, UDIPI ANIRUDDHA NAGENDRAN, JOUPPI NORMAN PAUL, BALASUBRAMONIAN RAJEEV
Year of Publication 09.12.2014

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Patent

MEMORY INTERFACE

MEMORY INTERFACE

by MURALIMANOHAR NAVEEN, DAVIS ALAN LYNN, UDIPI ANIRUDDHA NAGENDRAN, JOUPPI NORMAN PAUL, BALASUBRAMONIAN RAJEEV
Year of Publication 12.12.2013

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Patent

THREE-DIMENSIONAL MEMORY MODULE ARCHITECTURES

THREE-DIMENSIONAL MEMORY MODULE ARCHITECTURES

by BINKERT NATHAN LORENZO, MCLAREN MORAY, AHN, JUNG HO, DAVIS ALAN LYNN, JOUPPI NORMAN PAUL
Year of Publication 31.08.2010

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Patent

THREE-DIMENSIONAL DIE STACKS WITH INTER-DEVICE AND INTRA-DEVICE OPTICAL INTERCONNECT

THREE-DIMENSIONAL DIE STACKS WITH INTER-DEVICE AND INTRA-DEVICE OPTICAL INTERCONNECT

by BINKERT NATHAN LORENZO, DAVIS ALAN LYNN, BEAUSOLEIL RAYMOND G, JOUPPI NORMAN PAUL
Year of Publication 05.08.2010

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Patent

PHOTONIC INTERCONNECTS FOR COMPUTER SYSTEM DEVICES

PHOTONIC INTERCONNECTS FOR COMPUTER SYSTEM DEVICES

by BINKERT NATHAN LORENZO, FIORENTINO MARCO, XU QIANFAN, BEAUSOLEIL RAYMOND G, SCHREIBER ROBERT SAMUEL, JOUPPI NORMAN PAUL
Year of Publication 05.07.2010

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Patent

ALL OPTICAL FAST DISTRIBUTED ARBITRATION IN A COMPUTER SYSTEM DEVICE

ALL OPTICAL FAST DISTRIBUTED ARBITRATION IN A COMPUTER SYSTEM DEVICE

by BINKERT NATHAN LORENZO, FIORENTINO MARCO, XU QIANFAN, BEAUSOLEIL RAYMOND G, SCHREIBER ROBERT SAMUEL, JOUPPI NORMAN PAUL
Year of Publication 02.07.2010

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Patent

LOW LATENCY MATRIX MULTIPLY UNIT

LOW LATENCY MATRIX MULTIPLY UNIT

by Jouppi, Norman Paul, Phelps, Andrew Everett
Year of Publication 12.09.2024

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Patent

Low latency matrix multiply unit

Low latency matrix multiply unit

by Jouppi, Norman Paul, Phelps, Andrew Everett
Year of Publication 21.05.2024

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Patent

Performing matrix multiplication in hardware

Performing matrix multiplication in hardware

by Jouppi, Norman Paul, Phelps, Andrew Everett
Year of Publication 21.05.2024

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Patent

Error Checking For Systolic Array Computation

Error Checking For Systolic Array Computation

by Jouppi, Norman Paul, Yoon, Doe Hyun
Year of Publication 22.02.2024

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Patent

Low latency matrix multiply unit

Low latency matrix multiply unit

by Jouppi, Norman Paul, Phelps, Andrew Everett
Year of Publication 20.02.2024

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Patent

LOW LATENCY MATRIX MULTIPLY UNIT

LOW LATENCY MATRIX MULTIPLY UNIT

by JOUPPI, Norman Paul, PHELPS, Andrew Everett
Year of Publication 24.01.2024

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Patent

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