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Method and structure for forming strained SI for CMOS devices

Method and structure for forming strained SI for CMOS devices

by Steegen, An L, Yang, Haining S, Zhang, Ying
Year of Publication 19.04.2011

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Patent

Method and structure for forming strained Si for CMOS devices

Method and structure for forming strained Si for CMOS devices

by Steegen, An L, Yang, Haining S, Zhang, Ying
Year of Publication 20.04.2010

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Patent

Method and structure for forming strained SI for CMOS devices

Method and structure for forming strained SI for CMOS devices

by Steegen, An L, Yang, Haining S, Zhang, Ying
Year of Publication 23.06.2009

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Patent

Method and structure for forming strained SI for CMOS devices

Method and structure for forming strained SI for CMOS devices

by Steegen, An L, Yang, Haining S, Zhang, Ying
Year of Publication 30.09.2008

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Patent

Selective silicon-on-insulator isolation structure and method

Selective silicon-on-insulator isolation structure and method

by Steegen, An L, Surendra, Maheswaran, Wann, Hsing-Jen, Zhang, Ying, Zach, Franz, Wong, Robert
Year of Publication 12.04.2011

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Patent

Method and structure for forming strained Si for CMOS devices

Method and structure for forming strained Si for CMOS devices

by Steegen, An L, Yang, Haining S, Zhang, Ying
Year of Publication 31.10.2006

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Patent

Trench sidewall passivation for lateral RIE in a selective silicon-on-insulator process flow

Trench sidewall passivation for lateral RIE in a selective silicon-on-insulator process flow

by Baiocco, Christopher V, Steegen, An L, Zhang, Ying
Year of Publication 25.07.2006

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Patent

FET gate structure with metal gate electrode and silicide contact

FET gate structure with metal gate electrode and silicide contact

by Ku, Victor, Steegen, An, Wann, Hsing-Jen C
Year of Publication 06.06.2006

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Patent

Dense SRAM cells with selective SOI

Dense SRAM cells with selective SOI

by Wann, Hsingjen, Zhang, Ying, Wong, Robert C, Steegen, An
Year of Publication 05.04.2005

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Patent

Silicide proximity structures for CMOS device performance improvements

Silicide proximity structures for CMOS device performance improvements

by Chidambarrao, Dureseti, Dokumaci, Omer H, Rengarajan, Rajesh, Steegen, An L
Year of Publication 22.03.2005

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Patent

Method of making strained semiconductor transistors having lattice-mismatched semiconductor regions underlying source and drain regions

Method of making strained semiconductor transistors having lattice-mismatched semiconductor regions underlying source and drain regions

by Chen, Huajie, Chidambarrao, Dureseti, Gluschenkov, Oleg G, Steegen, An L, Yang, Haining S
Year of Publication 08.07.2008

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Patent

Process options of forming silicided metal gates for advanced CMOS devices

Process options of forming silicided metal gates for advanced CMOS devices

by Amos, Ricky S, Buchanan, Douglas A, Cabral, Jr, Cyril, Gousev, Evgeni P, Ku, Victor, Steegen, An
Year of Publication 05.02.2008

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Patent

Selective silicon-on-insulator isolation structure and method

Selective silicon-on-insulator isolation structure and method

by Steegen, An L, Surendra, Maheswaran, Wann, Hsing-Jen, Zhang, Ying, Zach, Franz, Wong, Robert
Year of Publication 05.02.2008

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Patent

Method of making strained semiconductor transistors having lattice-mismatched semiconductor regions underlying source and drain regions

Method of making strained semiconductor transistors having lattice-mismatched semiconductor regions underlying source and drain regions

by Chen, Huajie, Chidambarrao, Dureseti, Gluschenkov, Oleg G, Steegen, An L, Yang, Haining S
Year of Publication 06.11.2007

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Patent

Process options of forming silicided metal gates for advanced CMOS devices

Process options of forming silicided metal gates for advanced CMOS devices

by Amos, Ricky S, Buchanan, Douglas A, Cabral, Jr, Cyril, Gousev, Evgeni P, Ku, Victor, Steegen, An
Year of Publication 18.04.2006

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Patent

Method of forming FET silicide gate structures incorporating inner spacers

Method of forming FET silicide gate structures incorporating inner spacers

by Ku, Victor, Steegen, An, Wann, Hsing-Jen C, Wong, Keith Kwong Hon
Year of Publication 13.12.2005

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Patent

Selective silicon-on-insulator isolation structure and method

Selective silicon-on-insulator isolation structure and method

by Steegen, An L, Surendra, Maheswaran, Wann, Hsing-Jen, Zhang, Ying, Zach, Franz, Wong, Robert
Year of Publication 30.08.2005

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Patent

Method for integration of silicide contacts and silicide gate metals

Method for integration of silicide contacts and silicide gate metals

by Cabral, Jr, Cyril, Kedzierski, Jakub T, Ku, Victor, Lavoie, Christian, Narayanan, Vijay, Steegen, An L
Year of Publication 09.08.2005

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Patent

Structure and method of making strained semiconductor CMOS transistors having lattice-mismatched semiconductor regions underlying source and drain regions

Structure and method of making strained semiconductor CMOS transistors having lattice-mismatched semiconductor regions underlying source and drain regions

by Chen, Huajie, Chidambarrao, Dureseti, Gluschenkov, Oleg G, Steegen, An L, Yang, Haining S
Year of Publication 10.05.2005

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Patent

CMOS silicide metal gate integration

CMOS silicide metal gate integration

by Amos, Ricky S, Boyd, Diane C, Cabral, Jr, Cyril, Kaplan, Richard D, Kedzierski, Jakub T, Ku, Victor, Lee, Woo-Hyeong, Li, Ying, Mocuta, Anda C, Narayanan, Vijay, Steegen, An L, Surendra, Maheswaren
Year of Publication 02.02.2010

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Patent