A 7 Gb/s half-rate clock and data recovery circuit with compact control loop
Yu-Po Cheng, Yen-Long Lee, Ming-Hung Chien, Soon-Jyh Chang
Published in 2016 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) (01.04.2016)
Published in 2016 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) (01.04.2016)
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Conference Proceeding
On The Development of a Legal Penalty Prediction System for Drunk Driving Cases
Wu, Meng-Luen, Lin, Chen, Yu, Po-Cheng
Published in 2022 International Conference on Machine Learning and Cybernetics (ICMLC) (09.09.2022)
Published in 2022 International Conference on Machine Learning and Cybernetics (ICMLC) (09.09.2022)
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Conference Proceeding
LDO Linear Regulator with Super-source Follower
Yi-Tsung Chang, Fu-Lian Hung, Ren-Hao Xue, Yu-Da Shiau, Po-Yu Cheng
Published in 2014 International Symposium on Computer, Consumer and Control (01.06.2014)
Published in 2014 International Symposium on Computer, Consumer and Control (01.06.2014)
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Conference Proceeding
A Fast and Jitter-Modulation Free Jitter Tolerance Estimation Technique for Bang- Bang CDRs
Lee, Yen-Long, Cheng, Yu-Po, Chang, Soon-Jyh, Ting, Hsin-Wen
Published in IEEE design and test (01.02.2018)
Published in IEEE design and test (01.02.2018)
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Magazine Article