1.5-V single work-function W/WN/n(+)-poly gate CMOS device design with 110-nm buried-channel PMOS for 90-nm vertical-cell DRAM
Rengarajan, R, He, B, Ransom, C, Choi, C J, Ramachandran, R, Yang, H, Butt, S, Halle, S, Yan, W, Lee, K, Chudzik, M
Published in IEEE electron device letters (01.10.2002)
Published in IEEE electron device letters (01.10.2002)
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Journal Article
1.5-V single work-function W/WN/n+-poly gate CMOS device design with 110-nm buried-channel PMOS for 90-nm vertical-cell DRAM
Rengarajan, R, He, Boyong, Ransom, C, Choi, Chang Ju, Ramachandran, R, Yang, Haining, Butt, S, Halle, S, Yan, W, Lee, K, Chudzik, M, Robl, W, Parks, C, Massey, J G, La Rosa, G, Li, Yujun, Radens, C, Divakaruni, R, Crabbe, E
Published in IEEE electron device letters (01.10.2002)
Published in IEEE electron device letters (01.10.2002)
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Journal Article
1.5-V single work-function W/WN/n/sup +/-poly gate CMOS device design with 110-nm buried-channel PMOS for 90-nm vertical-cell DRAM
Rengarajan, R., Boyong He, Ransom, C., Chang Ju Choi, Ramachandran, R., Haining Yang, Butt, S., Halle, S., Yan, W., Lee, K., Chudzik, M., Robl, W., Parks, C., Massey, J.G., La Rosa, G., Yujun Li, Radens, C., Divakaruni, R., Crabbe, E.
Published in IEEE electron device letters (01.10.2002)
Published in IEEE electron device letters (01.10.2002)
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Journal Article
Channel hot-electron and hot-hole improvement in Al and Cu multilevel metal CMOS using deuterated anneals and passivating films
Clark, W.F., Cottrell, P.E., Ference, T.G., Lo, S.H., Massey, J.G., Mittl, S.W., Rankin, J.H.
Published in International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318) (1999)
Published in International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318) (1999)
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