Limited switch dynamic logic circuits for high-speed low-power circuit design
Belluomini, W., Jamsek, D., Martin, A. K., McDowell, C., Montoye, R. K., Ngo, H. C., Sawada, J.
Published in IBM journal of research and development (01.03.2006)
Published in IBM journal of research and development (01.03.2006)
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Journal Article
A decompression core for PowerPC
Kemp, T. M., Montoye, R. K., Harper, J. D., Palmer, J. D., Auerbach, D. J.
Published in IBM journal of research and development (01.11.1998)
Published in IBM journal of research and development (01.11.1998)
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Journal Article
Second-generation RISC floating point with multiply-add fused
Hokenek, E., Montoye, R.K., Cook, P.W.
Published in IEEE journal of solid-state circuits (01.10.1990)
Published in IEEE journal of solid-state circuits (01.10.1990)
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Journal Article
An 8T-SRAM for Variability Tolerance and Low-Voltage Operation in High-Performance Caches
Chang, L., Montoye, R.K., Nakamura, Y., Batson, K.A., Eickemeyer, R.J., Dennard, R.H., Haensch, W., Jamsek, D.
Published in IEEE journal of solid-state circuits (01.04.2008)
Published in IEEE journal of solid-state circuits (01.04.2008)
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