A Decision-Error-Tolerant 45 nm CMOS 7b 1 GS/s Nonbinary 2b/Cycle SAR ADC
Hyeok-Ki Hong, Wan Kim, Hyun-Wook Kang, Sun-Jae Park, Choi, Michael, Ho-Jin Park, Seung-Tak Ryu
Published in IEEE journal of solid-state circuits (01.02.2015)
Published in IEEE journal of solid-state circuits (01.02.2015)
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Journal Article
A 0.6 V 12 b 10 MS/s Low-Noise Asynchronous SAR-Assisted Time-Interleaved SAR (SATI-SAR) ADC
Kim, Wan, Hong, Hyeok-Ki, Roh, Yi-Ju, Kang, Hyun-Wook, Hwang, Sun-Il, Jo, Dong-Shin, Chang, Dong-Jin, Seo, Min-Jae, Ryu, Seung-Tak
Published in IEEE journal of solid-state circuits (01.08.2016)
Published in IEEE journal of solid-state circuits (01.08.2016)
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Journal Article
A Sign-Equality-Based Background Timing-Mismatch Calibration Algorithm for Time-Interleaved ADCs
Kang, Hyun-Wook, Hong, Hyeok-Ki, Park, Sanghoon, Kim, Ki-Jin, Ahn, Kwang-Ho, Ryu, Seung-Tak
Published in IEEE transactions on circuits and systems. II, Express briefs (01.06.2016)
Published in IEEE transactions on circuits and systems. II, Express briefs (01.06.2016)
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Journal Article
A 65 nm 0.08-to-680 MHz Low-Power Synthesizable MDLL With Nested-Delay Cell and Background Static Phase Offset Calibration
Chang, Dong-Jin, Seo, Min-Jae, Hong, Hyeok-Ki, Ryu, Seung-Tak
Published in IEEE transactions on circuits and systems. II, Express briefs (01.03.2018)
Published in IEEE transactions on circuits and systems. II, Express briefs (01.03.2018)
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Journal Article
26.7 A 2.6b/cycle-architecture-based 10b 1 JGS/s 15.4mW 4-time-interleaved SAR ADC with a multistep hardware-retirement technique
Hong, Hyeok-Ki, Kang, Hyun-Wook, Jo, Dong-Shin, Lee, Dong-Suk, You, Yong-Sang, Lee, Yong-Hee, Park, Ho-Jin, Ryu, Seung-Tak
Published in 2015 IEEE International Solid State Circuits Conference (ISSCC) (01.02.2015)
Published in 2015 IEEE International Solid State Circuits Conference (ISSCC) (01.02.2015)
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