Next generation spin torque memories

This book offers detailed insights into spin transfer torque (STT) based devices, circuits and memories. Starting with the basic concepts and device physics, it then addresses advanced STT applications and discusses the outlook for this cutting-edge technology. It also describes the architectures, p...

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Bibliographic Details
Main Author Kaushik, Brajesh Kumar
Other Authors Verma, Shivam (Writer on microelectronics), Kulkarni, Anant Aravind, Prajapati, Sanjay
Format Electronic eBook
LanguageEnglish
Published Singapore : Springer, [2017]
SeriesSpringerBriefs in applied sciences and technology.
Subjects
Spintronics.
Nanotechnology.
Microelectronics.
elektronické knihy
electronic books
Online AccessPlný text

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Table of Contents:
  • Preface; Contents; About the Authors; 1 Emerging Memory Technologies; 1.1 Introduction; 1.2 Non-volatile Memories; 1.2.1 Phase Change Memory; 1.2.2 Resistive RAM; 1.2.3 Ferroelectric RAM; 1.2.4 Magnetoresistive RAM; 1.3 Spin Torque Based Memories; 1.3.1 Spin Transfer Torque MRAM; 1.3.2 Spin Orbit Torque MRAM; 1.3.3 Domain Wall MRAM; 1.4 Comparison of Emerging Memory Technologies; 1.5 Chapter Summary; References; 2 Next Generation 3-D Spin Transfer Torque Magneto-resistive Random Access Memories; 2.1 Overview of Conventional STT MRAM: Architecture and Operation; 2.2 Cell Size in Memories.
  • 2.3 Next Generation 4F2 STT MRAM2.3.1 Proposed Architecture; 2.3.2 Performance Parameters and Windows; 2.3.3 Simulation Framework; 2.4 Case Study; 2.4.1 TCAD Analysis; 2.4.2 TCAD Simulation Setup; 2.4.3 Mixed-Mode Simulation Results; 2.4.4 Impact of High-k GAA Devices; 2.4.5 Impact of High-k GD on Delay; 2.5 Proposed Fabrication Methodology; 2.6 Conclusion; References; 3 Spin Orbit Torque MRAM; 3.1 Introduction; 3.2 SOT Device Structure; 3.3 SOT-MRAM Bit-Cell and Array Architectures; 3.4 SOT-MRAM Write and Read Mechanisms; 3.4.1 Concept of Simultaneous Read and Write Operations.
  • 3.5 Compact Modeling of the SOT-MTJ Device3.5.1 Magnetization Dynamics; 3.5.2 TMR; 3.6 Design Aspects and Performance Optimization of SOT-MRAM; 3.7 Comparative Analysis of STT-MRAM and SOT-MRAM; References; 4 Multilevel Cell MRAMs; 4.1 Introduction; 4.2 Issues with Single Level Cell (SLC) STT-/SOT-MRAM; 4.3 Multilevel Cell (MLC) Configurations; 4.3.1 STT Based MLC Configurations; 4.3.2 SOT Based MLC Configurations; 4.4 Multilevel Cell (MLC) MRAM Operations; 4.4.1 MLC STT-MRAM Write and Read Operations; 4.4.2 MLC SOT-MRAM Write and Read Operation; 4.5 Modeling and Simulation of MLC MRAMs.
  • 4.5.1 Simulations of MLC MRAMs4.6 Design Aspects and Optimization of MLC MRAMs; 4.6.1 sMLC MRAMs; 4.6.2 pMLC MRAMs; 4.7 Conclusions; References; 5 Magnetic Domain Wall Race Track Memory; 5.1 Introduction; 5.1.1 Limitations of Existing and Emerging Memory Technologies; 5.2 Fundamentals of Domain-Wall Motion in Nanowire; 5.2.1 Magnetic Domains in Magnetic Nanowire; 5.2.2 Domain-Wall Motion in Nanowire; 5.2.3 Optimization of Domain Wall Motion; 5.3 Domain Wall MRAM; 5.3.1 DW-MRAM Write and Read Operations; 5.4 Racetrack Memory; 5.4.1 Structure of Racetrack Memory; 5.4.2 Write and Read Operations.
  • 5.5 Racetrack Memory Based Logic Implementations5.6 Chapter Summary; References.

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